//! ************************************************************************** // Written by: Map P.20131013 on Wed Jan 10 17:03:07 2024 //! ************************************************************************** SCHEMATIC START; COMP "rxn" LOCATE = SITE "L4" LEVEL 1; COMP "rxp" LOCATE = SITE "L3" LEVEL 1; COMP "txn" LOCATE = SITE "K2" LEVEL 1; COMP "txp" LOCATE = SITE "K1" LEVEL 1; COMP "spill" LOCATE = SITE "AC22" LEVEL 1; COMP "dtc_trig_n<10>" LOCATE = SITE "AJ16" LEVEL 1; COMP "dtc_trig_n<11>" LOCATE = SITE "AL19" LEVEL 1; COMP "dtc_trig_n<12>" LOCATE = SITE "AD20" LEVEL 1; COMP "dtc_trig_n<20>" LOCATE = SITE "AK32" LEVEL 1; COMP "dtc_trig_n<13>" LOCATE = SITE "AG21" LEVEL 1; COMP "dtc_trig_n<21>" LOCATE = SITE "AG30" LEVEL 1; COMP "dtc_trig_n<14>" LOCATE = SITE "AD19" LEVEL 1; COMP "dtc_trig_n<22>" LOCATE = SITE "AP33" LEVEL 1; COMP "dtc_trig_n<30>" LOCATE = SITE "AF33" LEVEL 1; COMP "dtc_trig_n<15>" LOCATE = SITE "AL24" LEVEL 1; COMP "dtc_trig_n<23>" LOCATE = SITE "AH32" LEVEL 1; COMP "dtc_trig_n<31>" LOCATE = SITE "R32" LEVEL 1; COMP "dtc_trig_n<16>" LOCATE = SITE "AJ27" LEVEL 1; COMP "dtc_trig_n<24>" LOCATE = SITE "V25" LEVEL 1; COMP "dtc_trig_n<32>" LOCATE = SITE "W34" LEVEL 1; COMP "dtc_trig_n<17>" LOCATE = SITE "AK24" LEVEL 1; COMP "dtc_trig_n<25>" LOCATE = SITE "AK34" LEVEL 1; COMP "dtc_trig_n<33>" LOCATE = SITE "Y34" LEVEL 1; COMP "dtc_trig_n<18>" LOCATE = SITE "AK28" LEVEL 1; COMP "dtc_trig_n<26>" LOCATE = SITE "AF31" LEVEL 1; COMP "dtc_trig_n<34>" LOCATE = SITE "U32" LEVEL 1; COMP "dtc_trig_n<19>" LOCATE = SITE "AG26" LEVEL 1; COMP "dtc_trig_n<27>" LOCATE = SITE "Y26" LEVEL 1; COMP "dtc_trig_n<35>" LOCATE = SITE "R34" LEVEL 1; COMP "dtc_trig_n<28>" LOCATE = SITE "AE32" LEVEL 1; COMP "dtc_trig_n<36>" LOCATE = SITE "P34" LEVEL 1; COMP "dtc_trig_n<29>" LOCATE = SITE "AC34" LEVEL 1; COMP "dtc_trig_n<37>" LOCATE = SITE "M33" LEVEL 1; COMP "dtc_trig_n<38>" LOCATE = SITE "K31" LEVEL 1; COMP "dtc_trig_n<39>" LOCATE = SITE "M32" LEVEL 1; COMP "dtc_trig_p<10>" LOCATE = SITE "AJ17" LEVEL 1; COMP "dtc_trig_p<11>" LOCATE = SITE "AK19" LEVEL 1; COMP "dtc_trig_p<12>" LOCATE = SITE "AC20" LEVEL 1; COMP "dtc_trig_p<20>" LOCATE = SITE "AK33" LEVEL 1; COMP "dtc_trig_p<13>" LOCATE = SITE "AG20" LEVEL 1; COMP "dtc_trig_p<21>" LOCATE = SITE "AF30" LEVEL 1; COMP "dtc_trig_p<14>" LOCATE = SITE "AC19" LEVEL 1; COMP "dtc_trig_p<22>" LOCATE = SITE "AP32" LEVEL 1; COMP "dtc_trig_p<30>" LOCATE = SITE "AE33" LEVEL 1; COMP "dtc_trig_p<15>" LOCATE = SITE "AK23" LEVEL 1; COMP "dtc_trig_p<23>" LOCATE = SITE "AH33" LEVEL 1; COMP "dtc_trig_p<31>" LOCATE = SITE "R31" LEVEL 1; COMP "dtc_trig_p<16>" LOCATE = SITE "AK27" LEVEL 1; COMP "dtc_trig_p<24>" LOCATE = SITE "W25" LEVEL 1; COMP "dtc_trig_p<32>" LOCATE = SITE "V34" LEVEL 1; COMP "dtc_trig_p<17>" LOCATE = SITE "AJ24" LEVEL 1; COMP "dtc_trig_p<25>" LOCATE = SITE "AL34" LEVEL 1; COMP "dtc_trig_p<33>" LOCATE = SITE "Y33" LEVEL 1; COMP "dtc_trig_p<18>" LOCATE = SITE "AL28" LEVEL 1; COMP "dtc_trig_p<26>" LOCATE = SITE "AG31" LEVEL 1; COMP "dtc_trig_p<34>" LOCATE = SITE "U33" LEVEL 1; COMP "dtc_trig_p<19>" LOCATE = SITE "AG25" LEVEL 1; COMP "dtc_trig_p<27>" LOCATE = SITE "AA25" LEVEL 1; COMP "dtc_trig_p<35>" LOCATE = SITE "R33" LEVEL 1; COMP "dtc_trig_p<28>" LOCATE = SITE "AD32" LEVEL 1; COMP "dtc_trig_p<36>" LOCATE = SITE "N34" LEVEL 1; COMP "dtc_trig_p<29>" LOCATE = SITE "AD34" LEVEL 1; COMP "dtc_trig_p<37>" LOCATE = SITE "N33" LEVEL 1; COMP "dtc_trig_p<38>" LOCATE = SITE "K32" LEVEL 1; COMP "dtc_trig_p<39>" LOCATE = SITE "L33" LEVEL 1; COMP "brd_reset_n" LOCATE = SITE "L9" LEVEL 1; COMP "sru_busy_flag_out_nim" LOCATE = SITE "AC23" LEVEL 1; COMP "test_pulse" LOCATE = SITE "AC24" LEVEL 1; COMP "sru_trig_synced_out_nim" LOCATE = SITE "AH9" LEVEL 1; COMP "dtc_return_n<0>" LOCATE = SITE "AH10" LEVEL 1; COMP "dtc_return_n<1>" LOCATE = SITE "AE12" LEVEL 1; COMP "dtc_return_n<2>" LOCATE = SITE "AE11" LEVEL 1; COMP "dtc_return_n<3>" LOCATE = SITE "AG13" LEVEL 1; COMP "dtc_return_n<4>" LOCATE = SITE "AE17" LEVEL 1; COMP "dtc_return_n<5>" LOCATE = SITE "AG17" LEVEL 1; COMP "dtc_return_n<6>" LOCATE = SITE "AF15" LEVEL 1; COMP "dtc_return_n<7>" LOCATE = SITE "AH12" LEVEL 1; COMP "dtc_return_n<8>" LOCATE = SITE "AG18" LEVEL 1; COMP "dtc_return_p<0>" LOCATE = SITE "AJ10" LEVEL 1; COMP "dtc_return_n<9>" LOCATE = SITE "AD21" LEVEL 1; COMP "dtc_return_p<1>" LOCATE = SITE "AE13" LEVEL 1; COMP "dtc_return_p<2>" LOCATE = SITE "AF11" LEVEL 1; COMP "dtc_return_p<3>" LOCATE = SITE "AF13" LEVEL 1; COMP "dtc_return_p<4>" LOCATE = SITE "AD17" LEVEL 1; COMP "dtc_return_p<5>" LOCATE = SITE "AH17" LEVEL 1; COMP "dtc_return_p<6>" LOCATE = SITE "AG15" LEVEL 1; COMP "dtc_return_p<7>" LOCATE = SITE "AG12" LEVEL 1; COMP "dtc_return_p<8>" LOCATE = SITE "AH18" LEVEL 1; COMP "dtc_return_p<9>" LOCATE = SITE "AE21" LEVEL 1; COMP "ttc_l1accept_n" LOCATE = SITE "G33" LEVEL 1; COMP "ttc_l1accept_p" LOCATE = SITE "F33" LEVEL 1; COMP "dtc_clk_n<0>" LOCATE = SITE "AP12" LEVEL 1; COMP "dtc_clk_n<1>" LOCATE = SITE "AJ12" LEVEL 1; COMP "dtc_clk_n<2>" LOCATE = SITE "AM11" LEVEL 1; COMP "dtc_clk_n<3>" LOCATE = SITE "AM13" LEVEL 1; COMP "dtc_clk_n<4>" LOCATE = SITE "AK16" LEVEL 1; COMP "dtc_clk_n<5>" LOCATE = SITE "AC17" LEVEL 1; COMP "dtc_clk_n<6>" LOCATE = SITE "AL14" LEVEL 1; COMP "dtc_clk_n<7>" LOCATE = SITE "AN14" LEVEL 1; COMP "dtc_clk_n<8>" LOCATE = SITE "AM16" LEVEL 1; COMP "dtc_clk_p<0>" LOCATE = SITE "AP11" LEVEL 1; COMP "dtc_clk_n<9>" LOCATE = SITE "AN18" LEVEL 1; COMP "dtc_clk_p<1>" LOCATE = SITE "AK12" LEVEL 1; COMP "dtc_clk_p<2>" LOCATE = SITE "AL11" LEVEL 1; COMP "dtc_clk_p<3>" LOCATE = SITE "AN13" LEVEL 1; COMP "dtc_clk_p<4>" LOCATE = SITE "AL16" LEVEL 1; COMP "dtc_clk_p<5>" LOCATE = SITE "AC18" LEVEL 1; COMP "dtc_clk_p<6>" LOCATE = SITE "AL15" LEVEL 1; COMP "dtc_clk_p<7>" LOCATE = SITE "AP14" LEVEL 1; COMP "dtc_clk_p<8>" LOCATE = SITE "AM17" LEVEL 1; COMP "dtc_clk_p<9>" LOCATE = SITE "AP19" LEVEL 1; COMP "brdclk_n" LOCATE = SITE "H9" LEVEL 1; COMP "brdclk_p" LOCATE = SITE "J9" LEVEL 1; COMP "spare<4>" LOCATE = SITE "L21" LEVEL 1; COMP "spare<5>" LOCATE = SITE "L20" LEVEL 1; COMP "spare<6>" LOCATE = SITE "C18" LEVEL 1; COMP "spare<7>" LOCATE = SITE "B18" LEVEL 1; COMP "spare<8>" LOCATE = SITE "K22" LEVEL 1; COMP "spare<9>" LOCATE = SITE "K21" LEVEL 1; COMP "sfp_rx_n" LOCATE = SITE "N4" LEVEL 1; COMP "sfp_rx_p" LOCATE = SITE "N3" LEVEL 1; COMP "sfp_tx_n" LOCATE = SITE "M2" LEVEL 1; COMP "sfp_tx_p" LOCATE = SITE "M1" LEVEL 1; COMP "ttc_bcntres" LOCATE = SITE "K27" LEVEL 1; COMP "tlu_clk40_n" LOCATE = SITE "V23" LEVEL 1; COMP "tlu_clk40_p" LOCATE = SITE "U23" LEVEL 1; COMP "ttc_dout<0>" LOCATE = SITE "L26" LEVEL 1; COMP "ttc_dout<1>" LOCATE = SITE "L25" LEVEL 1; COMP "ttc_dout<2>" LOCATE = SITE "H32" LEVEL 1; COMP "ttc_dout<3>" LOCATE = SITE "G32" LEVEL 1; COMP "ttc_dout<4>" LOCATE = SITE "J34" LEVEL 1; COMP "ttc_dout<5>" LOCATE = SITE "K33" LEVEL 1; COMP "ttc_dout<6>" LOCATE = SITE "D32" LEVEL 1; COMP "ttc_dout<7>" LOCATE = SITE "D31" LEVEL 1; COMP "ttc_doutstr" LOCATE = SITE "J31" LEVEL 1; COMP "ttc_reset_b" LOCATE = SITE "B34" LEVEL 1; COMP "dtc_return_n<10>" LOCATE = SITE "AF16" LEVEL 1; COMP "dtc_return_n<11>" LOCATE = SITE "AE19" LEVEL 1; COMP "dtc_return_n<12>" LOCATE = SITE "AJ22" LEVEL 1; COMP "dtc_return_n<20>" LOCATE = SITE "AJ32" LEVEL 1; COMP "dtc_return_n<13>" LOCATE = SITE "AJ21" LEVEL 1; COMP "dtc_return_n<21>" LOCATE = SITE "AN34" LEVEL 1; COMP "dtc_return_n<14>" LOCATE = SITE "AH20" LEVEL 1; COMP "dtc_return_n<22>" LOCATE = SITE "AL33" LEVEL 1; COMP "dtc_return_n<30>" LOCATE = SITE "AF34" LEVEL 1; COMP "dtc_return_n<15>" LOCATE = SITE "AL25" LEVEL 1; COMP "dtc_return_n<23>" LOCATE = SITE "AD26" LEVEL 1; COMP "dtc_return_n<31>" LOCATE = SITE "P26" LEVEL 1; COMP "dtc_return_n<16>" LOCATE = SITE "AJ25" LEVEL 1; COMP "dtc_return_n<24>" LOCATE = SITE "W32" LEVEL 1; COMP "dtc_return_n<32>" LOCATE = SITE "U30" LEVEL 1; COMP "dtc_return_n<17>" LOCATE = SITE "AJ26" LEVEL 1; COMP "dtc_return_n<25>" LOCATE = SITE "AH34" LEVEL 1; COMP "dtc_return_n<33>" LOCATE = SITE "V33" LEVEL 1; COMP "dtc_return_n<18>" LOCATE = SITE "AK29" LEVEL 1; COMP "dtc_return_n<26>" LOCATE = SITE "AG32" LEVEL 1; COMP "dtc_return_n<34>" LOCATE = SITE "T34" LEVEL 1; COMP "dtc_return_n<19>" LOCATE = SITE "AH28" LEVEL 1; COMP "dtc_return_n<27>" LOCATE = SITE "AB33" LEVEL 1; COMP "dtc_return_n<35>" LOCATE = SITE "T25" LEVEL 1; COMP "dtc_return_n<28>" LOCATE = SITE "AC32" LEVEL 1; COMP "dtc_return_n<36>" LOCATE = SITE "L34" LEVEL 1; COMP "dtc_return_n<29>" LOCATE = SITE "AA33" LEVEL 1; COMP "dtc_return_n<37>" LOCATE = SITE "P32" LEVEL 1; COMP "dtc_return_n<38>" LOCATE = SITE "L31" LEVEL 1; COMP "dtc_return_n<39>" LOCATE = SITE "P30" LEVEL 1; COMP "dtc_return_p<10>" LOCATE = SITE "AG16" LEVEL 1; COMP "dtc_return_p<11>" LOCATE = SITE "AF19" LEVEL 1; COMP "dtc_return_p<12>" LOCATE = SITE "AK22" LEVEL 1; COMP "dtc_return_p<20>" LOCATE = SITE "AJ31" LEVEL 1; COMP "dtc_return_p<13>" LOCATE = SITE "AK21" LEVEL 1; COMP "dtc_return_p<21>" LOCATE = SITE "AN33" LEVEL 1; COMP "dtc_return_p<14>" LOCATE = SITE "AJ20" LEVEL 1; COMP "dtc_return_p<22>" LOCATE = SITE "AM33" LEVEL 1; COMP "dtc_return_p<30>" LOCATE = SITE "AE34" LEVEL 1; COMP "dtc_return_p<15>" LOCATE = SITE "AM25" LEVEL 1; COMP "dtc_return_p<23>" LOCATE = SITE "AD25" LEVEL 1; COMP "dtc_return_p<31>" LOCATE = SITE "P25" LEVEL 1; COMP "dtc_return_p<16>" LOCATE = SITE "AH25" LEVEL 1; COMP "dtc_return_p<24>" LOCATE = SITE "W31" LEVEL 1; COMP "dtc_return_p<32>" LOCATE = SITE "U31" LEVEL 1; COMP "dtc_return_p<17>" LOCATE = SITE "AK26" LEVEL 1; COMP "dtc_return_p<25>" LOCATE = SITE "AJ34" LEVEL 1; COMP "dtc_return_p<33>" LOCATE = SITE "V32" LEVEL 1; COMP "dtc_return_p<18>" LOCATE = SITE "AL29" LEVEL 1; COMP "dtc_return_p<26>" LOCATE = SITE "AG33" LEVEL 1; COMP "dtc_return_p<34>" LOCATE = SITE "T33" LEVEL 1; COMP "dtc_return_p<19>" LOCATE = SITE "AH27" LEVEL 1; COMP "dtc_return_p<27>" LOCATE = SITE "AC33" LEVEL 1; COMP "dtc_return_p<35>" LOCATE = SITE "U25" LEVEL 1; COMP "dtc_return_p<28>" LOCATE = SITE "AB32" LEVEL 1; COMP "dtc_return_p<36>" LOCATE = SITE "K34" LEVEL 1; COMP "dtc_return_p<29>" LOCATE = SITE "AA34" LEVEL 1; COMP "dtc_return_p<37>" LOCATE = SITE "N32" LEVEL 1; COMP "dtc_return_p<38>" LOCATE = SITE "M31" LEVEL 1; COMP "dtc_return_p<39>" LOCATE = SITE "P31" LEVEL 1; COMP "FLASH_RS0" LOCATE = SITE "AA23" LEVEL 1; COMP "FLASH_RS1" LOCATE = SITE "AG23" LEVEL 1; COMP "sru_trig_out_nim" LOCATE = SITE "AJ9" LEVEL 1; COMP "FLASH_A<10>" LOCATE = SITE "D9" LEVEL 1; COMP "FLASH_A<11>" LOCATE = SITE "C9" LEVEL 1; COMP "FLASH_A<12>" LOCATE = SITE "D10" LEVEL 1; COMP "FLASH_A<20>" LOCATE = SITE "AF10" LEVEL 1; COMP "FLASH_A<13>" LOCATE = SITE "C10" LEVEL 1; COMP "FLASH_A<21>" LOCATE = SITE "AF9" LEVEL 1; COMP "FLASH_A<14>" LOCATE = SITE "F10" LEVEL 1; COMP "FLASH_A<22>" LOCATE = SITE "AL9" LEVEL 1; COMP "FLASH_A<15>" LOCATE = SITE "F9" LEVEL 1; COMP "FLASH_A<16>" LOCATE = SITE "AH8" LEVEL 1; COMP "FLASH_A<17>" LOCATE = SITE "AG8" LEVEL 1; COMP "FLASH_A<18>" LOCATE = SITE "AP9" LEVEL 1; COMP "FLASH_A<19>" LOCATE = SITE "AN9" LEVEL 1; COMP "FLASH_DQ<0>" LOCATE = SITE "AF24" LEVEL 1; COMP "FLASH_DQ<1>" LOCATE = SITE "AF25" LEVEL 1; COMP "FLASH_DQ<2>" LOCATE = SITE "W24" LEVEL 1; COMP "FLASH_DQ<3>" LOCATE = SITE "V24" LEVEL 1; COMP "FLASH_DQ<4>" LOCATE = SITE "H24" LEVEL 1; COMP "FLASH_DQ<5>" LOCATE = SITE "H25" LEVEL 1; COMP "FLASH_DQ<6>" LOCATE = SITE "P24" LEVEL 1; COMP "FLASH_DQ<7>" LOCATE = SITE "R24" LEVEL 1; COMP "FLASH_DQ<8>" LOCATE = SITE "G23" LEVEL 1; COMP "FLASH_DQ<9>" LOCATE = SITE "H23" LEVEL 1; COMP "LedIndicator<0>" LOCATE = SITE "C22" LEVEL 1; COMP "LedIndicator<1>" LOCATE = SITE "D22" LEVEL 1; COMP "LedIndicator<2>" LOCATE = SITE "G26" LEVEL 1; COMP "LedIndicator<3>" LOCATE = SITE "H10" LEVEL 1; COMP "dtc_data_n<0>" LOCATE = SITE "AC12" LEVEL 1; COMP "dtc_data_n<1>" LOCATE = SITE "AK11" LEVEL 1; COMP "dtc_data_n<2>" LOCATE = SITE "AL10" LEVEL 1; COMP "dtc_data_n<3>" LOCATE = SITE "AN12" LEVEL 1; COMP "dtc_data_n<4>" LOCATE = SITE "AK17" LEVEL 1; COMP "dtc_data_n<5>" LOCATE = SITE "AD15" LEVEL 1; COMP "dtc_data_n<6>" LOCATE = SITE "AJ14" LEVEL 1; COMP "dtc_data_n<7>" LOCATE = SITE "AL13" LEVEL 1; COMP "dtc_data_n<8>" LOCATE = SITE "AP17" LEVEL 1; COMP "dtc_data_p<0>" LOCATE = SITE "AC13" LEVEL 1; COMP "dtc_data_n<9>" LOCATE = SITE "AL18" LEVEL 1; COMP "dtc_data_p<1>" LOCATE = SITE "AJ11" LEVEL 1; COMP "dtc_data_p<2>" LOCATE = SITE "AM10" LEVEL 1; COMP "dtc_data_p<3>" LOCATE = SITE "AM12" LEVEL 1; COMP "dtc_data_p<4>" LOCATE = SITE "AK18" LEVEL 1; COMP "dtc_data_p<5>" LOCATE = SITE "AC15" LEVEL 1; COMP "dtc_data_p<6>" LOCATE = SITE "AK14" LEVEL 1; COMP "dtc_data_p<7>" LOCATE = SITE "AK13" LEVEL 1; COMP "dtc_data_p<8>" LOCATE = SITE "AN17" LEVEL 1; COMP "dtc_data_p<9>" LOCATE = SITE "AM18" LEVEL 1; COMP "dtc_clk_n<10>" LOCATE = SITE "AP15" LEVEL 1; COMP "dtc_clk_n<11>" LOCATE = SITE "AF21" LEVEL 1; COMP "dtc_clk_n<12>" LOCATE = SITE "AL20" LEVEL 1; COMP "dtc_clk_n<20>" LOCATE = SITE "AK31" LEVEL 1; COMP "dtc_clk_n<13>" LOCATE = SITE "AN23" LEVEL 1; COMP "dtc_clk_n<21>" LOCATE = SITE "AE26" LEVEL 1; COMP "dtc_clk_n<14>" LOCATE = SITE "AL23" LEVEL 1; COMP "dtc_clk_n<22>" LOCATE = SITE "AM31" LEVEL 1; COMP "dtc_clk_n<30>" LOCATE = SITE "AC29" LEVEL 1; COMP "dtc_clk_n<15>" LOCATE = SITE "AP24" LEVEL 1; COMP "dtc_clk_n<23>" LOCATE = SITE "AE29" LEVEL 1; COMP "dtc_clk_n<31>" LOCATE = SITE "T26" LEVEL 1; COMP "dtc_clk_n<16>" LOCATE = SITE "AH24" LEVEL 1; COMP "dtc_clk_n<24>" LOCATE = SITE "W26" LEVEL 1; COMP "dtc_clk_n<32>" LOCATE = SITE "V27" LEVEL 1; COMP "dtc_clk_n<17>" LOCATE = SITE "AP26" LEVEL 1; COMP "dtc_clk_n<25>" LOCATE = SITE "AH30" LEVEL 1; COMP "dtc_clk_n<33>" LOCATE = SITE "Y29" LEVEL 1; COMP "dtc_clk_n<18>" LOCATE = SITE "AM28" LEVEL 1; COMP "dtc_clk_n<26>" LOCATE = SITE "AC25" LEVEL 1; COMP "dtc_clk_n<34>" LOCATE = SITE "V29" LEVEL 1; COMP "dtc_clk_n<19>" LOCATE = SITE "AP31" LEVEL 1; COMP "dtc_clk_n<27>" LOCATE = SITE "AA29" LEVEL 1; COMP "dtc_clk_n<35>" LOCATE = SITE "T31" LEVEL 1; COMP "dtc_clk_n<28>" LOCATE = SITE "AC27" LEVEL 1; COMP "dtc_clk_n<36>" LOCATE = SITE "R29" LEVEL 1; COMP "dtc_clk_n<29>" LOCATE = SITE "AB31" LEVEL 1; COMP "dtc_clk_n<37>" LOCATE = SITE "L30" LEVEL 1; COMP "dtc_clk_n<38>" LOCATE = SITE "M27" LEVEL 1; COMP "dtc_clk_n<39>" LOCATE = SITE "M28" LEVEL 1; COMP "dtc_clk_p<10>" LOCATE = SITE "AP16" LEVEL 1; COMP "dtc_clk_p<11>" LOCATE = SITE "AF20" LEVEL 1; COMP "dtc_clk_p<12>" LOCATE = SITE "AM20" LEVEL 1; COMP "dtc_clk_p<20>" LOCATE = SITE "AL31" LEVEL 1; COMP "dtc_clk_p<13>" LOCATE = SITE "AP22" LEVEL 1; COMP "dtc_clk_p<21>" LOCATE = SITE "AF26" LEVEL 1; COMP "dtc_clk_p<14>" LOCATE = SITE "AM23" LEVEL 1; COMP "dtc_clk_p<22>" LOCATE = SITE "AL30" LEVEL 1; COMP "dtc_clk_p<30>" LOCATE = SITE "AD29" LEVEL 1; COMP "dtc_clk_p<15>" LOCATE = SITE "AP25" LEVEL 1; COMP "dtc_clk_p<23>" LOCATE = SITE "AE28" LEVEL 1; COMP "dtc_clk_p<31>" LOCATE = SITE "R26" LEVEL 1; COMP "dtc_clk_p<16>" LOCATE = SITE "AH23" LEVEL 1; COMP "dtc_clk_p<24>" LOCATE = SITE "W27" LEVEL 1; COMP "dtc_clk_p<32>" LOCATE = SITE "V28" LEVEL 1; COMP "dtc_clk_p<17>" LOCATE = SITE "AP27" LEVEL 1; COMP "dtc_clk_p<25>" LOCATE = SITE "AH29" LEVEL 1; COMP "dtc_clk_p<33>" LOCATE = SITE "W29" LEVEL 1; COMP "dtc_clk_p<18>" LOCATE = SITE "AN28" LEVEL 1; COMP "dtc_clk_p<26>" LOCATE = SITE "AB25" LEVEL 1; COMP "dtc_clk_p<34>" LOCATE = SITE "U28" LEVEL 1; COMP "dtc_clk_p<19>" LOCATE = SITE "AP30" LEVEL 1; COMP "dtc_clk_p<27>" LOCATE = SITE "AA28" LEVEL 1; COMP "dtc_clk_p<35>" LOCATE = SITE "T30" LEVEL 1; COMP "dtc_clk_p<28>" LOCATE = SITE "AB27" LEVEL 1; COMP "dtc_clk_p<36>" LOCATE = SITE "P29" LEVEL 1; COMP "dtc_clk_p<29>" LOCATE = SITE "AB30" LEVEL 1; COMP "dtc_clk_p<37>" LOCATE = SITE "L29" LEVEL 1; COMP "dtc_clk_p<38>" LOCATE = SITE "M26" LEVEL 1; COMP "dtc_clk_p<39>" LOCATE = SITE "L28" LEVEL 1; COMP "sfp_refclk_n" LOCATE = SITE "M5" LEVEL 1; COMP "sfp_refclk_p" LOCATE = SITE "M6" LEVEL 1; COMP "FPGA_PROG_B" LOCATE = SITE "J32" LEVEL 1; COMP "sru_busy_flag_out_n" LOCATE = SITE "T23" LEVEL 1; COMP "sru_busy_flag_out_p" LOCATE = SITE "T24" LEVEL 1; COMP "dtc_trig_n<0>" LOCATE = SITE "AD11" LEVEL 1; COMP "dtc_trig_n<1>" LOCATE = SITE "AC14" LEVEL 1; COMP "dtc_trig_n<2>" LOCATE = SITE "AG10" LEVEL 1; COMP "dtc_trig_n<3>" LOCATE = SITE "AF14" LEVEL 1; COMP "dtc_trig_n<4>" LOCATE = SITE "AF18" LEVEL 1; COMP "dtc_trig_n<5>" LOCATE = SITE "AD16" LEVEL 1; COMP "dtc_trig_n<6>" LOCATE = SITE "AH15" LEVEL 1; COMP "dtc_trig_n<7>" LOCATE = SITE "AH14" LEVEL 1; COMP "dtc_trig_n<8>" LOCATE = SITE "AH19" LEVEL 1; COMP "dtc_trig_p<0>" LOCATE = SITE "AD12" LEVEL 1; COMP "dtc_trig_n<9>" LOCATE = SITE "AH22" LEVEL 1; COMP "dtc_trig_p<1>" LOCATE = SITE "AD14" LEVEL 1; COMP "dtc_trig_p<2>" LOCATE = SITE "AG11" LEVEL 1; COMP "dtc_trig_p<3>" LOCATE = SITE "AE14" LEVEL 1; COMP "dtc_trig_p<4>" LOCATE = SITE "AE18" LEVEL 1; COMP "dtc_trig_p<5>" LOCATE = SITE "AE16" LEVEL 1; COMP "dtc_trig_p<6>" LOCATE = SITE "AJ15" LEVEL 1; COMP "dtc_trig_p<7>" LOCATE = SITE "AH13" LEVEL 1; COMP "dtc_trig_p<8>" LOCATE = SITE "AJ19" LEVEL 1; COMP "dtc_trig_p<9>" LOCATE = SITE "AG22" LEVEL 1; COMP "htrig_nim" LOCATE = SITE "AD22" LEVEL 1; COMP "spare<10>" LOCATE = SITE "A19" LEVEL 1; COMP "spare<11>" LOCATE = SITE "A18" LEVEL 1; COMP "ttc_ready" LOCATE = SITE "D34" LEVEL 1; COMP "ttc_saddr<0>" LOCATE = SITE "H33" LEVEL 1; COMP "ttc_saddr<1>" LOCATE = SITE "H34" LEVEL 1; COMP "ttc_saddr<2>" LOCATE = SITE "K29" LEVEL 1; COMP "ttc_saddr<3>" LOCATE = SITE "J30" LEVEL 1; COMP "ttc_saddr<4>" LOCATE = SITE "F34" LEVEL 1; COMP "ttc_saddr<5>" LOCATE = SITE "E34" LEVEL 1; COMP "ttc_saddr<6>" LOCATE = SITE "E31" LEVEL 1; COMP "ttc_saddr<7>" LOCATE = SITE "F31" LEVEL 1; COMP "ttc_evcntres" LOCATE = SITE "K26" LEVEL 1; COMP "htrig_number_n" LOCATE = SITE "AE24" LEVEL 1; COMP "htrig_number_p" LOCATE = SITE "AD24" LEVEL 1; COMP "FLASH_A<0>" LOCATE = SITE "AL8" LEVEL 1; COMP "FLASH_A<1>" LOCATE = SITE "AK8" LEVEL 1; COMP "FLASH_A<2>" LOCATE = SITE "AC9" LEVEL 1; COMP "FLASH_A<3>" LOCATE = SITE "AD10" LEVEL 1; COMP "FLASH_A<4>" LOCATE = SITE "C8" LEVEL 1; COMP "FLASH_A<5>" LOCATE = SITE "B8" LEVEL 1; COMP "FLASH_A<6>" LOCATE = SITE "E9" LEVEL 1; COMP "FLASH_A<7>" LOCATE = SITE "E8" LEVEL 1; COMP "FLASH_A<8>" LOCATE = SITE "A8" LEVEL 1; COMP "FLASH_A<9>" LOCATE = SITE "A9" LEVEL 1; COMP "FLASH_CS_B" LOCATE = SITE "Y24" LEVEL 1; COMP "FLASH_OE_B" LOCATE = SITE "AA24" LEVEL 1; COMP "FLASH_WE_B" LOCATE = SITE "AF23" LEVEL 1; COMP "FLASH_DQ<10>" LOCATE = SITE "N24" LEVEL 1; COMP "FLASH_DQ<11>" LOCATE = SITE "N23" LEVEL 1; COMP "FLASH_DQ<12>" LOCATE = SITE "F23" LEVEL 1; COMP "FLASH_DQ<13>" LOCATE = SITE "F24" LEVEL 1; COMP "FLASH_DQ<14>" LOCATE = SITE "L24" LEVEL 1; COMP "FLASH_DQ<15>" LOCATE = SITE "M23" LEVEL 1; COMP "dtc_data_n<10>" LOCATE = SITE "AM15" LEVEL 1; COMP "dtc_data_n<11>" LOCATE = SITE "AP21" LEVEL 1; COMP "dtc_data_n<12>" LOCATE = SITE "AN20" LEVEL 1; COMP "dtc_data_n<20>" LOCATE = SITE "AJ30" LEVEL 1; COMP "dtc_data_n<13>" LOCATE = SITE "AN22" LEVEL 1; COMP "dtc_data_n<21>" LOCATE = SITE "AG28" LEVEL 1; COMP "dtc_data_n<14>" LOCATE = SITE "AL21" LEVEL 1; COMP "dtc_data_n<22>" LOCATE = SITE "AM32" LEVEL 1; COMP "dtc_data_n<30>" LOCATE = SITE "AC30" LEVEL 1; COMP "dtc_data_n<15>" LOCATE = SITE "AN24" LEVEL 1; COMP "dtc_data_n<23>" LOCATE = SITE "AD27" LEVEL 1; COMP "dtc_data_n<31>" LOCATE = SITE "R27" LEVEL 1; COMP "dtc_data_n<16>" LOCATE = SITE "AM27" LEVEL 1; COMP "dtc_data_n<24>" LOCATE = SITE "Y27" LEVEL 1; COMP "dtc_data_n<32>" LOCATE = SITE "W30" LEVEL 1; COMP "dtc_data_n<17>" LOCATE = SITE "AM26" LEVEL 1; COMP "dtc_data_n<25>" LOCATE = SITE "AF29" LEVEL 1; COMP "dtc_data_n<33>" LOCATE = SITE "Y31" LEVEL 1; COMP "dtc_data_n<18>" LOCATE = SITE "AP29" LEVEL 1; COMP "dtc_data_n<26>" LOCATE = SITE "AB26" LEVEL 1; COMP "dtc_data_n<34>" LOCATE = SITE "U27" LEVEL 1; COMP "dtc_data_n<19>" LOCATE = SITE "AM30" LEVEL 1; COMP "dtc_data_n<27>" LOCATE = SITE "AD31" LEVEL 1; COMP "dtc_data_n<35>" LOCATE = SITE "T29" LEVEL 1; COMP "dtc_data_n<28>" LOCATE = SITE "AC28" LEVEL 1; COMP "dtc_data_n<36>" LOCATE = SITE "N30" LEVEL 1; COMP "dtc_data_n<29>" LOCATE = SITE "AA31" LEVEL 1; COMP "dtc_data_n<37>" LOCATE = SITE "N29" LEVEL 1; COMP "dtc_data_n<38>" LOCATE = SITE "M25" LEVEL 1; COMP "dtc_data_n<39>" LOCATE = SITE "P27" LEVEL 1; COMP "dtc_data_p<10>" LOCATE = SITE "AN15" LEVEL 1; COMP "dtc_data_p<11>" LOCATE = SITE "AP20" LEVEL 1; COMP "dtc_data_p<12>" LOCATE = SITE "AN19" LEVEL 1; COMP "dtc_data_p<20>" LOCATE = SITE "AJ29" LEVEL 1; COMP "dtc_data_p<13>" LOCATE = SITE "AM22" LEVEL 1; COMP "dtc_data_p<21>" LOCATE = SITE "AG27" LEVEL 1; COMP "dtc_data_p<14>" LOCATE = SITE "AM21" LEVEL 1; COMP "dtc_data_p<22>" LOCATE = SITE "AN32" LEVEL 1; COMP "dtc_data_p<30>" LOCATE = SITE "AD30" LEVEL 1; COMP "dtc_data_p<15>" LOCATE = SITE "AN25" LEVEL 1; COMP "dtc_data_p<23>" LOCATE = SITE "AE27" LEVEL 1; COMP "dtc_data_p<31>" LOCATE = SITE "R28" LEVEL 1; COMP "dtc_data_p<16>" LOCATE = SITE "AN27" LEVEL 1; COMP "dtc_data_p<24>" LOCATE = SITE "Y28" LEVEL 1; COMP "dtc_data_p<32>" LOCATE = SITE "V30" LEVEL 1; COMP "dtc_data_p<17>" LOCATE = SITE "AL26" LEVEL 1; COMP "dtc_data_p<25>" LOCATE = SITE "AF28" LEVEL 1; COMP "dtc_data_p<33>" LOCATE = SITE "Y32" LEVEL 1; COMP "dtc_data_p<18>" LOCATE = SITE "AN29" LEVEL 1; COMP "dtc_data_p<26>" LOCATE = SITE "AA26" LEVEL 1; COMP "dtc_data_p<34>" LOCATE = SITE "U26" LEVEL 1; COMP "dtc_data_p<19>" LOCATE = SITE "AN30" LEVEL 1; COMP "dtc_data_p<27>" LOCATE = SITE "AE31" LEVEL 1; COMP "dtc_data_p<35>" LOCATE = SITE "T28" LEVEL 1; COMP "dtc_data_p<28>" LOCATE = SITE "AB28" LEVEL 1; COMP "dtc_data_p<36>" LOCATE = SITE "M30" LEVEL 1; COMP "dtc_data_p<29>" LOCATE = SITE "AA30" LEVEL 1; COMP "dtc_data_p<37>" LOCATE = SITE "N28" LEVEL 1; COMP "dtc_data_p<38>" LOCATE = SITE "N25" LEVEL 1; COMP "dtc_data_p<39>" LOCATE = SITE "N27" LEVEL 1; MACRO "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gtx_reset_gen/hset" LOCATE = SITE "SLICE_X0Y120:SLICE_X105Y159" LEVEL 1; COMPGRP udp_mac.SLICE = COMP "u_udp_mac/reset_synch" COMP "u_sru_trigger/tlu_event_number<3>" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata256" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata303" COMP "u_udp_mac/u_udp_fsm/tdata<3>2" COMP "event_number<55>" COMP "u_udp_mac/u_udp_fsm/tdata<4>2" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata_83" COMP "u_udp_mac/u_udp_fsm/tdata<3>5" COMP "event_number<3>" COMP "event_number<7>" COMP "u_sru_trigger/tlu_event_number_shift<16>" COMP "event_number_fifo_rd_en" COMP "u_udp_mac/u_udp_fsm/tdata<4>5" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata_91" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata_71" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata307" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata25" COMP "u_udp_mac/u_udp_fsm/running_packet_count<5>" COMP "u_udp_mac/u_udp_fsm/state<2>2" COMP "u_udp_mac/u_udp_fsm/state<2>1" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata_7" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata_82" COMP "u_udp_mac/u_udp_fsm/tdata<4>9" COMP "u_sru_cmd_par/walign_reg<19>" COMP "u_udp_mac/u_udp_fsm/tdata<2>2" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata301" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata253" COMP "packet_trace<3>" COMP "u_udp_mac/u_udp_fsm/tdata<3>10" COMP "u_udp_mac/u_udp_fsm/tdata<2>1" COMP "u_udp_mac/u_udp_fsm/state_FSM_FFd4" COMP "u_udp_mac/u_udp_fsm/state_FSM_FFd5" COMP "u_udp_mac/u_udp_fsm/tdata<5>3" COMP "u_udp_mac/u_udp_fsm/current_packet_count<3>" COMP "u_udp_mac/u_udp_fsm/reset_state[4]_OR_1508_o" COMP "u_udp_mac/u_udp_fsm/tdata<5>5" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata_93" COMP "u_udp_mac/u_udp_fsm/tdata<5>9" COMP "u_udp_mac/u_udp_fsm/tdata<3>1" COMP "packet_trace<9>" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata_10" COMP "u_udp_mac/u_udp_fsm/state_FSM_FFd5-In1" COMP "u_udp_mac/u_udp_fsm/current_packet_count<7>" COMP "u_udp_mac/u_udp_fsm/current_packet_count<9>" COMP "u_udp_mac/u_udp_fsm/state_FSM_FFd3" COMP "u_udp_mac/tdata<2>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/ip_tx_int_data_data_out<7>" COMP "u_udp_mac/u_udp_fsm/Mmux_tdata_101" COMP "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_addr<0>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/ip_tx_int_data_data_out<0>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/Mmux__n0222_47" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/Mmux__n0222_31" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/Mmux_ip_tx_data_data_out113" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/GND_747_o_PWR_275_o_mux_8_OUT[1]21" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/GND_747_o_tx_count[15]_equal_19_o<15>12" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B41" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_rs_A<6>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_rs_A<13>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/ip_tx_int_data_data_out<5>" COMP "packet_trace<25>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/GND_751_o_ip_tx_hdr_data_length[15]_LessThan_5_o22" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/Mmux__n0222_3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_rs_A<0>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B51" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B71" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B201" COMP "packet_trace<21>" COMP "packet_trace<29>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/GND_747_o_PWR_275_o_mux_8_OUT[1]" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/ip_tx_int_data_data_out<4>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/ip_tx_int_data_data_out<1>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_rs_B<0>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/Mmux__n0222_37" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/Mmux__n0222_36" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/Mmux__n0222_32" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_rs_A<12>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B181" COMP "packet_trace<13>" COMP "u_udp_mac/u_udp_fsm/state_FSM_FFd5-In2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B18" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/udp_tx_state_FSM_FFd1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/udp_tx_state_FSM_FFd2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/crc_state_FSM_FFd4" COMP "packet_trace<37>" COMP "u_udp_mac/u_udp_fsm/last_packet" COMP "u_udp_mac/tuser<15>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_rs_A<4>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_rs_A<10>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B61" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/crc_state_FSM_FFd2" COMP "packet_trace<33>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B22" COMP "u_udp_mac/u_udp_fsm/state_FSM_FFd1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out202" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/ip_tx_int_hdr_data_length<2>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_rs_B<4>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/_n0229<16>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/N47" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/N23" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out129" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_0_BRB3" COMP "packet_trace<17>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out322" COMP "size_rd_en" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B5" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_rs_B<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_mode<1>_inv_inv" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/PWR_275_o_GND_747_o_mux_30_OUT[0]" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/ip_tx_start_int" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out285" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux__n0451_73" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out47" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_8_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_30_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_21_BRB3" COMP "packet_trace<67>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data<6>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold<4>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold<2>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/crc_state_FSM_FFd3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out41" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B121" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out293" COMP "udp_ip_lsbs<5>" COMP "packet_trace<73>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold<6>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out162" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out207" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out86" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out85" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out245" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out326" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out281" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out325" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out324" COMP "packet_trace<229>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B23" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B20" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_crc_state[3]_X_747_o_wide_mux_149_OUT_B7" COMP "udp_ip_lsbs<1>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/GND_751_o_tx_count[15]_equal_29_o<15>1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out24" COMP "udp_ip_lsbs<4>" COMP "packet_trace<43>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out283" COMP "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/Mmux_dout_mux35" COMP "udp_ip_lsbs<7>" COMP "packet_trace<165>" COMP "packet_trace<97>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/GND_751_o_PWR_279_o_mux_8_OUT[1]<31>2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data<1>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold<0>" COMP "packet_trace<89>" COMP "packet_trace<63>" COMP "packet_trace<59>" COMP "packet_trace<123>" COMP "packet_trace<93>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux__n0451_79" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<4>4" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<3>6" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<6>4" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<2>5" COMP "packet_trace<137>" COMP "packet_trace<101>" COMP "packet_trace<131>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out43" COMP "u_sru_cmd_par/Mmux_GND_76_o_GND_76_o_mux_366_OUT1813" COMP "packet_trace<55>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out1631" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<7>4" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux__n0451_71" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<5>_bdd10" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/N268" COMP "packet_trace<235>" COMP "packet_trace<107>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_req_int_ip<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_req_int_ip<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/N2" COMP "packet_trace<127>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/ip_tx_result_int<1>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_mac_data_out<6>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out20" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<1>7" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<4>5" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<5>4" COMP "packet_trace<77>" COMP "packet_trace<205>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/GND_751_o_PWR_279_o_mux_8_OUT[1]<31>" COMP "packet_trace<225>" COMP "u_udp_mac/tready" COMP "packet_trace<161>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/ip_tx_result_int<0>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/ip_mac_valid" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<6>5" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_mac_data_out<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_mac_data_out<4>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_mac_data_out<2>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<2>6" COMP "packet_trace<47>" COMP "packet_trace<141>" COMP "packet_trace<243>" COMP "packet_trace<247>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/ip_mac_req" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_mac_grant" COMP "packet_trace<217>" COMP "u_udp_mac/u_udp_fsm/byte_counter<15>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<3>7" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer_enable<31>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler<15>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler<22>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer_enable<31>3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler<26>" COMP "packet_trace<111>" COMP "packet_trace<81>" COMP "packet_trace<175>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/_n0269_inv" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data<2>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_req_int_ip<11>" COMP "packet_trace<213>" COMP "u_udp_mac/u_udp_fsm/byte_counter<3>" COMP "u_udp_mac/u_udp_fsm/byte_counter<11>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<0>6" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<5>5" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count[7]_rx_count[7]_OR_1631_o12" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer_enable<31>4" COMP "packet_trace<145>" COMP "packet_trace<209>" COMP "packet_trace<149>" COMP "packet_trace<119>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_state_FSM_FFd3" COMP "packet_trace<183>" COMP "packet_trace<221>" COMP "u_udp_mac/u_udp_fsm/byte_counter<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timeout_reg" COMP "packet_trace<187>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count[7]_rx_count[7]_OR_1631_o26" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<0>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count[7]_rx_count[7]_OR_1631_o13" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Mcount_timer_lut<0>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/set_timeout<1>_inv21" COMP "packet_trace<239>" COMP "packet_trace<85>" COMP "packet_trace<51>" COMP "packet_trace<255>" COMP "packet_trace<191>" COMP "packet_trace<153>" COMP "packet_trace<157>" COMP "u_sru_cmd_par/Mmux_GND_76_o_GND_76_o_mux_366_OUT1712" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count[7]_rx_count[7]_OR_1631_o32" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_req_int_lookup_req" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux__n0451_72" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/set_timer<0>_inv_inv" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_state_FSM_FFd2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/_n0766_inv" COMP "packet_trace<115>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_tx_tready" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/tx_reset" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/N20" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_state_FSM_FFd1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<28>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<16>" COMP "packet_trace<179>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/N27" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_req_int_ip<23>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_req_int_ip<27>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/N21" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_state_FSM_FFd2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_mac_req" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_state_FSM_FFd2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count[7]_rx_count[7]_OR_1631_o19" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux__n0451_74" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_state_FSM_FFd3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/force_burst2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tlast_reg" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_req_int_ip<19>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_req_int_ip<15>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_req_int_ip<31>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<1>1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/N6" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count[7]_rx_count[7]_OR_1631_o25" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux__n0451_76" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux__n0451_78" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/txcharisk_r" COMP "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/force_assert" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/two_byte_tx" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/SYNC_TX_RESET_I/R2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<6>6" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_state_FSM_FFd1-In1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_mac_data_out<1>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out_valid_bdd3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux_mac_data_out16" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<4>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd10" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/ignore_packet" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/no_burst" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd8" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr<27>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<36>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux__n0451_66" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux__n0451_6" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<32>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<24>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/force_end" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/early_underrun" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd7" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr<11>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr<15>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr<19>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr<23>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr<31>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<1>11" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_valid_reg" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux__n0451_63" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<20>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mmux__n0451_61" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<12>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<8>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/_n0762_inv" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/txchardispval_r" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip<11>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<0>1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip<31>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<6>3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<7>3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<40>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_rslt_int_mac<25>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_rslt_int_mac<27>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<31>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<23>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_rslt_int_mac<23>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found<26>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_gtxtest_bit1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr[10]_GND_64_o_equal_2_o" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip<15>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip<23>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip<19>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_0_BRB1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_reply_required" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<44>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<4>3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac<47>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_29_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_31_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_20_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_23_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rxrundisp_r" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rxclkcorcnt_r<2>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gtx_resetn_inv" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/SYNC_RX_RESET_I/R2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_7_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_12_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_16_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip<27>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_6_BRB1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<3>4" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_14_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found<17>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found<32>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_26_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_31_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rxnotintable_r" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_data_reg<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_rx_tdata<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/INT_GLBL_RST" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rx_reset" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_1_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_20_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_17_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_25_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_is_valid" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_rslt_int_mac<36>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<15>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_15_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_rslt_int_mac<32>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_29_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/Mcompar_tx_count[15]_udp_txi_hdr_data_length[15]_equal_43_o_cy<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count[15]_udp_txi_hdr_data_length[15]_equal_43_o" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gmii_rxd_int<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gmii_rxd_int<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_data_reg<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/mgt_tx_data_r<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_rx_tdata<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_11_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_operation<1>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_0_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_19_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/reset_inv" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_30_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found<41>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<3>2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_28_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<11>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_rslt_int_mac<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Mcompar_tx_count[15]_ip_tx_hdr_data_length[15]_equal_87_o_cy<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/reset_r<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_5_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_state_FSM_FFd2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Mmux_set_arp_oper131" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_24_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_8_BRB0" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_rslt_int_mac<38>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<4>2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/data_out<2>2" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found<9>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/arp_req_rslt_int_mac<5>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr<10>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_state[1]_rx_enable_AND_13_o" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_state_FSM_FFd1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_rx_tvalid" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gtx_resetn" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<47>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found<46>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<27>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_10_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_frame_complete" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_3_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count_mode<0>_inv_inv" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_7_BRB1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac<47>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_13_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_16_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<19>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_2_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_27_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac<39>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<39>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_25_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_1_BRB1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_6_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_24_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_1_BRB3" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_count<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_count<7>" COMP "u_udp_mac/u_udp_fsm/Result<3>_FRB" COMP "u_udp_mac/u_udp_fsm/Result<7>_FRB" COMP "u_udp_mac/u_udp_fsm/Result<11>_FRB" COMP "u_udp_mac/u_udp_fsm/Result<15>_FRB" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Mcompar_req_ip_addr[31]_arp_entry_ip[31]_equal_10_o_cy<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Mcompar_req_ip_addr[31]_arp_entry_ip[31]_equal_10_o_cy<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<43>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac<35>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac<35>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac<43>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks<11>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks<15>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks<19>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks<23>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Madd_tx_hdr_cks[23]_GND_751_o_add_147_OUT_cy<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Madd_tx_hdr_cks[23]_GND_751_o_add_147_OUT_cy<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Madd_tx_hdr_cks[23]_GND_751_o_add_147_OUT_cy<11>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Madd_tx_hdr_cks[23]_GND_751_o_add_147_OUT_cy<15>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Madd_tx_hdr_cks[23]_GND_751_o_add_147_OUT_cy<19>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks[23]_GND_751_o_add_147_OUT<23>" COMP "u_udp_mac/u_udp_fsm/Msub_GND_739_o_GND_739_o_sub_73_OUT_cy<3>" COMP "u_udp_mac/u_udp_fsm/Msub_GND_739_o_GND_739_o_sub_73_OUT_cy<7>" COMP "u_udp_mac/u_udp_fsm/Msub_GND_739_o_GND_739_o_sub_73_OUT_cy<11>" COMP "u_udp_mac/u_udp_fsm/Msub_GND_739_o_GND_739_o_sub_73_OUT_cy<15>" COMP "u_udp_mac/u_udp_fsm/GND_739_o_GND_739_o_sub_73_OUT<16>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Msub_GND_753_o_GND_753_o_sub_31_OUT<31:0>_cy<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Msub_GND_753_o_GND_753_o_sub_31_OUT<31:0>_cy<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Msub_GND_753_o_GND_753_o_sub_31_OUT<31:0>_cy<11>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Msub_GND_753_o_GND_753_o_sub_31_OUT<31:0>_cy<15>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Msub_GND_753_o_GND_753_o_sub_31_OUT<31:0>_cy<19>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Msub_GND_753_o_GND_753_o_sub_31_OUT<31:0>_cy<23>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Mcompar_arp_entry_ip[31]_arp_req_req_ip[31]_equal_1_o_cy<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/Mcompar_arp_entry_ip[31]_arp_req_req_ip[31]_equal_1_o_cy<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip[31]_arp_req_req_ip[31]_equal_1_o_l1" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count<11>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count<15>" COMP "u_udp_mac/tuser<6>" COMP "u_udp_mac/tuser<10>" COMP "u_udp_mac/tuser<14>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/Madd_total_length_cy<6>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/Madd_total_length_cy<14>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Madd_total_length_cy<5>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Madd_total_length_cy<9>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/Madd_total_length_cy<13>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count<11>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count<15>" COMP "u_udp_mac/u_udp_fsm/Mcompar_GND_739_o_GND_739_o_equal_74_o_cy<3>" COMP "u_udp_mac/tlast" COMP "u_udp_mac/u_udp_fsm/Result<3>2_FRB" COMP "u_udp_mac/u_udp_fsm/Result<7>1_FRB" COMP "u_udp_mac/u_udp_fsm/Result<9>1_FRB" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count<3>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count<7>" COMP "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/plllkdet_sync"; COMPGRP "udp_mac.SLICE" LOCATE = SITE "SLICE_X0Y120:SLICE_X105Y159" LEVEL 4; COMPGRP slow_control.SLICE = COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_valid_pipe<1>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_valid_pipe<1>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<0>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_dcs_eth_top/u_udp_reply_mux/UdpSt_FSM_FFd2" COMP "u_dcs_eth_top/u_udp_reply_mux/UdpSt_FSM_FFd1-In111" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<2>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_sw_tx_fifo_status<3>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_reload_inv" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_dcs_eth_top/u_udp_reply_mux/UdpSt_FSM_FFd3" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_sw_wr_data_valid" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_sw_wr_enable" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_en" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<2>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/rd_sof_n_i" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "udp_tx_rd_fifo_addr<0>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mcount_rd_frames_lut<0>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/fifo_cs_i" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe<7>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<2>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/rd_eof_n_i" COMP "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd4-In4" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<7>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3-In2" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/fifo_cs_i" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_dcs_eth_top/ip_tx_rd_data_out<7>" COMP "u_dcs_eth_top/ip_tx_rd_data_out<5>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_dv_pipe<1>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_en" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_dcs_eth_top/ip_tx_rd_data_out<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_dcs_eth_top/u_udp_reply_mux/reset_synch" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_valid" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_dcs_eth_top/ip_tx_rd_data_out<1>" COMP "u_dcs_eth_top/ip_tx_rd_data_out<0>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/rd_sof_n_i" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_valid" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<129>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<189>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<137>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<183>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<156>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<161>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<169>" COMP "u_FlashToUDP/u_scController/scRplyQueue/df_din<40>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_good_frame" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<143>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<149>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<176>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_ch_sel" COMP "u_dcs_eth_top/u_ip_reply_fsm/_n0161_inv" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<123>" COMP "u_dcs_eth_top/u_arp_reply_fsm/ArpSt_FSM_FFd2" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt<4>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i<20>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/fifo_cs_i" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<76>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_rd_dst_rdy_n" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/fifo_cs" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<68>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/ArpSt_FSM_FFd3" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<85>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<122>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<223>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<196>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<67>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<71>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i<29>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<114>" COMP "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<1>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<79>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<56>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<60>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<64>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<118>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<213>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<221>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<201>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i<12>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/_n0098_inv" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<75>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<72>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<93>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<106>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<110>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<217>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<205>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<141>" COMP "u_dcs_eth_top/arp_tx_reply_frame<19>" COMP "u_dcs_eth_top/arp_tx_reply_frame<11>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/rd_eof_n_i" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<81>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<102>" COMP "u_dcs_eth_top/arp_tx_reply_frame<15>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<135>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<209>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<142>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<85>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<95>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<105>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<115>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<124>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<133>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<141>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<125>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<35>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<117>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<101>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<119>" COMP "u_dcs_eth_top/arp_tx_reply_frame<23>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<31>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<131>" COMP "u_dcs_eth_top/arp_tx_reply_frame<3>" COMP "u_dcs_eth_top/arp_tx_reply_frame<35>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<109>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<80>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<89>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<97>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<15>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<58>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<15>" COMP "u_dcs_eth_top/arp_tx_reply_frame<31>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<137>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<149>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<157>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<113>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<48>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<75>" COMP "u_dcs_eth_top/arp_tx_reply_frame<27>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<129>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<121>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<105>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<45>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<27>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<52>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_good_frame" COMP "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd4" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<83>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<145>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<43>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<153>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<63>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<41>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<54>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/st_FSM_FFd1" COMP "u_dcs_eth_top/arp_tx_reply_frame<43>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<49>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<23>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_HeaderUpdate" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<59>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<51>" COMP "u_dcs_eth_top/arp_tx_reply_frame<51>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<32>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg<36>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/st_FSM_FFd3" COMP "u_dcs_eth_top/arp_tx_reply_frame<59>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<39>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<44>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<16>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<8>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd3" COMP "u_dcs_eth_top/N8" COMP "u_dcs_eth_top/arp_tx_reply_frame<39>" COMP "u_dcs_eth_top/arp_tx_reply_frame<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/rd_sof_n_i" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<31>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd3-In1" COMP "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd4-In1" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<159>" COMP "u_dcs_eth_top/Eth_reply_rd_sof_n" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<28>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<19>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<23>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<12>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<19>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<27>" COMP "u_dcs_eth_top/u_ip_reply_fsm/_n0233" COMP "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd3-In3" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<67>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<47>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<79>" COMP "u_dcs_eth_top/arp_tx_reply_frame<79>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<36>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<24>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<20>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<75>" COMP "u_dcs_eth_top/arp_tx_reply_frame<47>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_en" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_good_frame" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<40>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe<32>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<35>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<63>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<55>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_dcs_eth_top/arp_tx_reply_frame<67>" COMP "u_dcs_eth_top/arp_tx_reply_frame<63>" COMP "u_dcs_eth_top/arp_tx_reply_frame<55>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe<71>" COMP "u_dcs_eth_top/arp_tx_reply_frame<71>" COMP "u_dcs_eth_top/Eth_reply_MAC<95>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/fifo_cs" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/rd_eof_n_i" COMP "udp_rxd<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<23>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<31>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<23>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<27>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<47>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<39>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<43>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<39>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_tog" COMP "u_dcs_eth_top/Eth_reply_MAC<91>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<47>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data<7>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<111>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_good_frame" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<35>" COMP "u_dcs_eth_top/arp_tx_reply_frame<75>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_store_frame_tog" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<43>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data<3>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<108>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data<5>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i<31>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<15>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i[47]_local_mac_i[47]_OR_143_o9" COMP "u_dcs_eth_top/Eth_reply_MAC<75>" COMP "u_dcs_eth_top/Eth_reply_MAC<83>" COMP "u_dcs_eth_top/Eth_reply_MAC<87>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<104>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i<23>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i<27>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<19>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i<31>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i[47]_local_mac_i[47]_OR_143_o8" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<92>" COMP "u_dcs_eth_top/Eth_reply_MAC<79>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<96>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<100>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data<1>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<15>_FRB" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i<15>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip<19>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip<31>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_eof_reg" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr<3>" COMP "u_dcs_eth_top/Eth_reply_MAC<71>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr<7>" COMP "u_dcs_eth_top/Eth_reply_MAC<67>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<3>_FRB" COMP "udp_rxd<3>" COMP "u_dcs_eth_top/ip_rd_data<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i<19>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip<27>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<15>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_eof" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr<11>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<84>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<88>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_dcs_eth_top/u_Eth_tx_fsm/EthReplySt_FSM_FFd3" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<24>" COMP "u_dcs_eth_top/icmp_frame" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/_n0526_inv1" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd3" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<40>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code<15>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_store_frame_tog" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_10_BRB1" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<55>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_11_BRB0" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/cnt<1>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/cnt<4>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip<15>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip<23>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<32>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type<15>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd2" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type[15]_GND_18_o_equal_105_o" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd1-In3" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<47>" COMP "u_dcs_eth_top/Eth_reply_rd_fifo_addr<0>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/cnt<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip<7>" COMP "u_dcs_eth_top/udp_frame" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd4" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_3" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type<15>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_equal_99_o" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_5_BRB0" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_8_BRB0" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_3" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code[15]_GND_18_o_equal_107_o<15>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_7_BRB2" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame_sync" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer<10>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_11_BRB2" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/IpSt_FSM_FFd1" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_state_FSM_FFd3" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/_n0583_inv" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol<7>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<18>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<36>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_equal_41_o" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_7" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_7" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<80>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<76>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/IpSt_FSM_FFd2" COMP "u_dcs_eth_top/ip_rd_data_valid" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_retran_frame_tog" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<28>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/ip_rd_ack" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/N6" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_equal_89_o" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_6_BRB1" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_2_BRB0" COMP "u_dcs_eth_top/Eth_reply_MAC<55>" COMP "u_dcs_eth_top/Eth_reply_MAC<59>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/EthReplySt_FSM_FFd1" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/UdpSt_FSM_FFd2" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_cnt<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_cnt<2>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/_n0583_inv2" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/_n0578_inv" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd4" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd1" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_7" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_5_BRB3" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt<10>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<64>" COMP "u_dcs_eth_top/Eth_reply_MAC<51>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<7>_FRB" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/IcmpSt_FSM_FFd3-In1" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_col_window_expire" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_tran_frame_tog" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd2" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr<1>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_accept_pipe<1>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd3" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<72>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg<68>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<11>_FRB" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/IcmpSt_FSM_FFd1" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_state_FSM_FFd4" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_4_BRB2" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer<6>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_4_BRB0" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt<15>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_sync" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/_n0151_inv" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/UdpSt_FSM_FFd1-In12" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/IcmpSt_FSM_FFd3" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_en" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpDataDv" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd1-In1" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_accept_bram" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checkState" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_reload" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_7" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr<11>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_valid" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_wr_enable" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg<43>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/frame_in_fifo" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr<4>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_enable_delay2" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2<15>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_3" COMP "u_dcs_eth_top/rx_ll_sof_n" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/RxllNewByte" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/frame_in_fifo_sync" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/ip_rd_enable" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_accept_pipe<1>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_data_pipe_st_FSM_FFd1" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_3" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_txfer_tog_delay" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray<5>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_dcs_eth_top/IPFrameLen<0>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr<8>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2<13>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_inc" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_fifo_full" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_rd_fifo_status<3>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame_delay" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_state_FSM_FFd3-In2" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<2>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_rx_fifo_status<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg<47>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr<0>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer<1>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray<10>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/N6" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray<10>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/N2" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length<0>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr<11>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray<6>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg<35>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_eof" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_state_reg" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg<8>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2<4>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_sof_pipe_0" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr<3>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr<7>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr<4>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg<39>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_state_FSM_FFd1" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync<11>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_sof_pipe_0" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr<0>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/N10" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr<8>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr<10>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_eof_reg" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg<31>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/N34" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg<12>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_fifo_full" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_sof_pipe_1" COMP "u_dcs_eth_top/rx_ll_src_rdy_n" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync<6>" COMP "u_dcs_eth_top/tx_ll_sof_n" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr[10]_GND_64_o_equal_2_o_inv" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_gtxtest_bit1" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/N18" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_16_count<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg<16>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_col_window_pipe<0>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/PWR_36_o_Eth_tx_fifo_status[3]_LessThan_3_o" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxchariscomma_r" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd3" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_col_window_pipe<1>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_col_window_expire" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_state_reg" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_ovflow_dst_rdy" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_bram_0" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_fifo_full" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray<11>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_state_FSM_FFd3" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr<1>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_fifo_status<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/txcharisk_r" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/reset_r<2>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_retransmit" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_data_i<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer<9>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd4" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_txfer_tog" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_eof_bram_0" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_state_FSM_FFd2" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_state_FSM_FFd1" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_pipe_1" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_accept_pipe<0>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_fifo_full" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_good_frame_r" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_data_valid_i" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/Mmux_rd_state[3]_tx_collision_MUX_183_o1" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd2" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_col_window_expire" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_tran_frame_tog" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr<1>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg<24>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_txfer_tog" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_dv_pipe<1>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_state_FSM_FFd3" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_pipe_0" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray<7>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_state_FSM_FFd2" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/Madd_chk_sum_i[31]_GND_42_o_add_4_OUT_cy<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/Madd_chk_sum_i[31]_GND_42_o_add_4_OUT_cy<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/Madd_chk_sum_i[31]_GND_42_o_add_4_OUT_cy<15>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/Madd_chk_sum_i[31]_GND_42_o_add_4_OUT_cy<19>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/Madd_chk_sum_i[31]_GND_42_o_add_4_OUT_cy<23>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/Madd_chk_sum_i[31]_GND_42_o_add_4_OUT_cy<27>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i[31]_GND_42_o_add_4_OUT<31>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r<3>" COMP "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_bad_frame_r" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_col_window_pipe<1>" COMP "u_dcs_eth_top/rx_ll_eof_n" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr<3>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr<7>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr<11>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_16_count<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_txfer_tog_delay" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_col_window_pipe<0>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_enable_delay" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_transmit_frame" COMP "u_dcs_eth_top/tx_ll_src_rdy_n" COMP "u_dcs_eth_top/tx_ll_eof_n" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_delay" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr<10>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames<3>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames<7>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames<8>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/resetdone_tx_r" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_txfer_tog" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/frame_in_fifo_sync" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames<6>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frame_in_fifo" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_bram_0" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_state_FSM_FFd1" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_ovflow_dst_rdy" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxclkcorcnt_r<2>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/resetdone_rx_r" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_txfer_tog_sync" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_tran_frame_sync" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_state_FSM_FFd2" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_reset_i" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_pipe_1" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_pipe_0" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/Mcompar_local_mac_i[47]_local_mac[47]_equal_101_o_cy<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/Mcompar_local_mac_i[47]_local_mac[47]_equal_101_o_cy<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/Mcompar_local_mac_i[47]_local_mac[47]_equal_101_o_cy<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i[47]_local_mac[47]_equal_101_o" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/resetdone_tx_r" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/resetdone_r" COMP "u_dcs_eth_top/rx_ll_reset" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i<4>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames<6>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frame_in_fifo" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_state_FSM_FFd2" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/resetdone_i" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/resetdone_rx_r" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_txfer_tog" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/Maccum_wr_frames_lut<6>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames<8>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_sof_pipe_1" COMP "u_dcs_eth_top/IPFrameLen<4>" COMP "u_dcs_eth_top/IPFrameLen<8>" COMP "u_dcs_eth_top/IPFrameLen<12>" COMP "u_dcs_eth_top/IPFrameLen<15>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/Madd_GND_23_o_GND_23_o_add_5_OUT_cy<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/Madd_GND_23_o_GND_23_o_add_5_OUT_cy<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/GND_23_o_GND_23_o_add_5_OUT<15>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_transmit_frame" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i<4>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_retran_frame_delay" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_tran_frame_delay" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_reset_i" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/frame_in_fifo" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_rd_pull_frame_AND_106_o_inv" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff<3>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff<7>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff<11>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames<8>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr<11>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/Madd_chk_sum_i[15]_chk_sum_i[31]_add_8_OUT_cy<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/Madd_chk_sum_i[15]_chk_sum_i[31]_add_8_OUT_cy<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/Madd_chk_sum_i[15]_chk_sum_i[31]_add_8_OUT_cy<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i[15]_chk_sum_i[31]_add_8_OUT<15>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff<11>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length<4>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length<8>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length<12>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length<15>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/Mcompar_arp_receiver_ip[31]_local_ip[31]_equal_112_o_cy<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/Mcompar_arp_receiver_ip[31]_local_ip[31]_equal_112_o_cy<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip[31]_local_ip[31]_equal_112_o" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/Mcompar_local_ip_i[31]_local_ip[31]_equal_120_o_cy<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/Mcompar_local_ip_i[31]_local_ip[31]_equal_120_o_cy<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i[31]_local_ip[31]_equal_120_o" COMP "u_dcs_eth_top/u_ip_reply_fsm/Mmux__n0139_rs_cy<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/Mmux__n0139_rs_cy<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/Mmux__n0139_rs_cy<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/_n0139<1>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/Mcompar_data_cnt[15]_IPFrameLen[15]_equal_27_o_cy<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/Madd_checksumC1_cy<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/Madd_checksumC1_cy<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC1<15>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr<11>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr<11>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr<11>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/Madd_rd_addr[11]_GND_24_o_add_164_OUT_cy<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr[11]_GND_24_o_add_164_OUT<11>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/Madd_rd_addr[11]_GND_24_o_add_164_OUT_cy<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/Madd_rd_addr[11]_GND_24_o_add_164_OUT_cy<7>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr<3>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr<7>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr<11>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt<7>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt<7>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt<11>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt<15>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_cnt<3>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_cnt<7>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer<3>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer<7>" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer<9>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/fifo_cs" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_tran_frame_delay" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame_tog" COMP "u_dcs_eth_top/tx_ll_data<4>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram<3>" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram<3>" COMP "u_dcs_eth_top/rx_ll_data<4>" COMP "u_FlashToUDP/u_UDPSCConv/reset_125" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_bf_pipe<1>" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/plllkdet_sync"; COMPGRP "slow_control.SLICE" LOCATE = SITE "SLICE_X0Y160:SLICE_X105Y199" LEVEL 4; COMPGRP slow_control.RAMB36 = COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen" COMP "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen" COMP "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen" COMP "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen"; COMPGRP "slow_control.RAMB36" LOCATE = SITE "RAMB36_X0Y32:RAMB36_X6Y39" LEVEL 4; COMPGRP dtc9_15_16_17_23_26_28_30.SLICE = COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_rd" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_rd" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/reset_40" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<0>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg<172>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<2>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/rdocmd_i<27>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<5>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt<4>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/reset_40" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" COMP "u_sru_40dtc_top/rdocmd_i<28>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "errcnt<369>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<10>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dina<743>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<0>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<4>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dina<750>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dina<739>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dina<967>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "errcnt<481>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<5>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dina<765>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dina<971>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "errcnt<449>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dina<978>" COMP "u_sru_40dtc_top/dina<751>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dina<747>" COMP "u_sru_40dtc_top/dina<760>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dina<907>" COMP "dtc_err_flag<23>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "errcnt<417>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "errcnt<493>" COMP "errcnt<381>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/reset_40" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dina<963>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dina<754>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dina<899>" COMP "u_sru_40dtc_top/dina<911>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dina<912>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<5>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/reset_serbitclkdiv" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dina<910>" COMP "u_sru_40dtc_top/dina<903>" COMP "dtc_err_flag<28>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "errcnt<429>" COMP "errcnt<485>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/DtcRamFlag_i<30>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "dtc_err_flag<26>" COMP "u_sru_40dtc_top/dina<974>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/DtcRamFlag_i<26>" COMP "errcnt<383>" COMP "errcnt<425>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dina<487>" COMP "u_sru_40dtc_top/dina<494>" COMP "errcnt<377>" COMP "errcnt<373>" COMP "u_sru_40dtc_top/dina<757>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<6>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dina<495>" COMP "u_sru_40dtc_top/dina<483>" COMP "u_sru_40dtc_top/dina<491>" COMP "errcnt<421>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dina<835>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dina<925>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<0>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dina<915>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dina<498>" COMP "u_sru_40dtc_top/dina<504>" COMP "errcnt<480>" COMP "errcnt<431>" COMP "u_sru_40dtc_top/wea<28>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<5>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "dtc_err_flag<17>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<0>" COMP "u_sru_40dtc_top/dina<509>" COMP "u_sru_40dtc_top/dina<861>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/wea<15>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "errcnt<489>" COMP "errcnt<461>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" COMP "errcnt<448>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/DtcRamFlag_i<17>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dina<839>" COMP "errcnt<453>" COMP "errcnt<457>" COMP "u_sru_40dtc_top/dina<555>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dina<916>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" COMP "u_sru_40dtc_top/dina<500>" COMP "u_sru_40dtc_top/dina<532>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/wea<17>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "errcnt<416>" COMP "u_sru_40dtc_top/dina<850>" COMP "u_sru_40dtc_top/dina<547>" COMP "errcnt<463>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<5>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/addra<144>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "dtc_err_flag<9>" COMP "errcnt<368>" COMP "u_sru_40dtc_top/DtcRamFlag_i<15>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dina<526>" COMP "u_sru_40dtc_top/dina<562>" COMP "u_sru_40dtc_top/dina<568>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dina<499>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/wea<23>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dina<302>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "dtc_err_flag<16>" COMP "u_sru_40dtc_top/dina<551>" COMP "errcnt<241>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "errcnt<265>" COMP "u_sru_40dtc_top/addra<248>" COMP "errcnt<257>" COMP "u_sru_40dtc_top/addra<252>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/addra<452>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/addra<448>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "errcnt<240>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dina<843>" COMP "u_sru_40dtc_top/addra<255>" COMP "errcnt<277>" COMP "errcnt<249>" COMP "u_sru_40dtc_top/addra<424>" COMP "u_sru_40dtc_top/addra<268>" COMP "u_sru_40dtc_top/addra<380>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_cmd_par/u_dtcout/Mmux_dtc_mon_sel[5]_dtc_deser_dout_i[0][15]_wide_mux_41_OUT_1311" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dina<309>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dina<984>" COMP "u_sru_40dtc_top/addra<368>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dina<847>" COMP "u_sru_40dtc_top/addra<240>" COMP "u_sru_40dtc_top/addra<244>" COMP "u_sru_40dtc_top/addra<376>" COMP "u_sru_40dtc_top/dina<530>" COMP "u_sru_40dtc_top/addra<383>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_cmd_par/u_dtcout/Mmux_dtc_mon_sel[5]_dtc_deser_dout_i[0][15]_wide_mux_41_OUT_132" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dina<527>" COMP "u_sru_40dtc_top/dina<519>" COMP "u_sru_40dtc_top/dina<536>" COMP "u_sru_40dtc_top/addra<264>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<0>" COMP "u_sru_40dtc_top/dina<573>" COMP "u_sru_40dtc_top/dina<501>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/addra<287>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dina<980>" COMP "u_sru_40dtc_top/wea<16>" COMP "u_sru_40dtc_top/addra<260>" COMP "errcnt<272>" COMP "errcnt<256>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<0>" COMP "u_sru_40dtc_top/dina<989>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dina<565>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/addra<488>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<8>" COMP "u_sru_40dtc_top/dina<317>" COMP "u_sru_40dtc_top/wea<30>" COMP "u_sru_40dtc_top/dina<295>" COMP "u_sru_40dtc_top/dina<852>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/addra<372>" COMP "u_sru_40dtc_top/addra<428>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/addra<460>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/addra<276>" COMP "u_sru_40dtc_top/addra<280>" COMP "u_sru_40dtc_top/addra<284>" COMP "u_sru_40dtc_top/addra<272>" COMP "u_sru_40dtc_top/dina<291>" COMP "u_sru_40dtc_top/dina<303>" COMP "u_sru_40dtc_top/dina<559>" COMP "errcnt<281>" COMP "u_sru_40dtc_top/wea<26>" COMP "u_sru_40dtc_top/addra<420>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<8>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/addra<152>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "errcnt<145>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dina<308>" COMP "dtc_err_flag<15>" COMP "u_sru_40dtc_top/dina<564>" COMP "errcnt<285>" COMP "errcnt<269>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_ram_wr_addr_1412" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dina<306>" COMP "u_sru_40dtc_top/dina<299>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "errcnt<153>" COMP "errcnt<261>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" COMP "u_sru_40dtc_top/dina<523>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/addra<463>" COMP "u_sru_40dtc_top/addra<484>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/addra<495>" COMP "u_sru_40dtc_top/addra<148>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/addra<156>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dina<856>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "errcnt<159>" COMP "u_sru_40dtc_top/dina<979>" COMP "u_sru_40dtc_top/dina<541>" COMP "u_sru_40dtc_top/dina<853>" COMP "errcnt<149>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/addra<456>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/addra<492>" COMP "u_sru_40dtc_top/addra<480>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/wea<9>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "errcnt<253>" COMP "u_sru_40dtc_top/dina<515>" COMP "errcnt<245>" COMP "errcnt<157>" COMP "u_sru_40dtc_top/dina<533>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>"; COMPGRP "dtc9_15_16_17_23_26_28_30.SLICE" LOCATE = SITE "SLICE_X0Y20:SLICE_X55Y59" LEVEL 4; COMPGRP dtc9_15_16_17_23_26_28_30.RAMB36 = COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"; COMPGRP "dtc9_15_16_17_23_26_28_30.RAMB36" LOCATE = SITE "RAMB36_X0Y4:RAMB36_X2Y11" LEVEL 4; COMPGRP dtc6_10.SLICE = COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/reset_40" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_rd" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/reset_bitclkdiv" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/reset_bitclkdiv" COMP "u_sru_40dtc_top/dina<195>" COMP "u_sru_40dtc_top/dina<206>" COMP "u_sru_40dtc_top/dina<199>" COMP "u_sru_40dtc_top/dina<221>" COMP "u_sru_40dtc_top/dina<216>" COMP "u_sru_40dtc_top/dina<210>" COMP "u_sru_40dtc_top/dina<213>" COMP "u_sru_40dtc_top/dina<338>" COMP "u_sru_cmd_par/Mmux_GND_76_o_GND_76_o_mux_366_OUT2843" COMP "u_sru_40dtc_top/dina<203>" COMP "u_sru_cmd_par/Mmux_GND_76_o_GND_76_o_mux_366_OUT630" COMP "u_sru_40dtc_top/dina<207>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dina<349>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>3" COMP "u_sru_40dtc_top/dina<211>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>11" COMP "u_sru_40dtc_top/dina<341>" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_ram_wr_addr_152" COMP "u_sru_40dtc_top/addra<96>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dina<327>" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_ram_wr_addr_0125" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/addra<111>" COMP "u_sru_40dtc_top/addra<100>" COMP "u_sru_40dtc_top/addra<104>" COMP "u_sru_40dtc_top/addra<108>" COMP "u_sru_40dtc_top/dina<212>" COMP "u_sru_40dtc_top/dina<323>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/wea<10>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>1" COMP "u_sru_40dtc_top/dina<335>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N4" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N4" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>2" COMP "u_sru_40dtc_top/dina<331>" COMP "u_sru_40dtc_top/dina<334>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/wea<6>" COMP "dtc_err_flag<6>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dina<340>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_cmd_par/udp_cmd_addr[15]_GND_76_o_equal_294_o<15>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/N6" COMP "u_sru_40dtc_top/dina<344>" COMP "u_sru_40dtc_top/dina<339>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3-In22" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "errcnt<161>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/DtcRamFlag_i<10>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "errcnt<169>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/DtcRamFlag_i<6>" COMP "u_sru_40dtc_top/addra<164>" COMP "u_sru_40dtc_top/addra<168>" COMP "u_sru_40dtc_top/addra<172>" COMP "u_sru_40dtc_top/addra<175>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "errcnt<165>" COMP "errcnt<160>" COMP "errcnt<173>" COMP "errcnt<175>" COMP "u_sru_40dtc_top/addra<160>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "errcnt<97>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "errcnt<101>" COMP "errcnt<111>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "errcnt<105>" COMP "errcnt<109>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In11" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In13" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/_n0069" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<3>2" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mcount_rd_frames_lut<0>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<0>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/N01" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<1>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<4>2" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<1>1" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_en" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<0>1" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>1" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/_n0069" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<4>1" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<8>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>2" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<4>2" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>2" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<1>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_reload_inv" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>"; COMPGRP "dtc6_10.SLICE" LOCATE = SITE "SLICE_X56Y59:SLICE_X105Y20" LEVEL 4; COMPGRP dtc4_5_8.SLICE = COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/reset_40" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_rd" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_wr" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dina<175>" COMP "u_sru_40dtc_top/dina<163>" COMP "u_sru_40dtc_top/dina<171>" COMP "u_sru_40dtc_top/rdocmd_i<11>" COMP "u_sru_40dtc_top/dina<189>" COMP "u_sru_40dtc_top/dina<146>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>3" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>11" COMP "u_sru_40dtc_top/dina<152>" COMP "u_sru_40dtc_top/dina<174>" COMP "u_sru_40dtc_top/dina<157>" COMP "u_sru_40dtc_top/dina<184>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/addra<84>" COMP "u_sru_40dtc_top/addra<88>" COMP "u_sru_40dtc_top/dina<274>" COMP "u_sru_40dtc_top/dina<181>" COMP "u_sru_40dtc_top/dina<148>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<5>1" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/addra<80>" COMP "u_sru_40dtc_top/addra<92>" COMP "u_sru_40dtc_top/addra<95>" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_ram_wr_addr_0124" COMP "u_sru_40dtc_top/dina<167>" COMP "u_sru_40dtc_top/dina<180>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<3>2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/addra<68>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dina<131>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/addra<64>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_en" COMP "u_sru_40dtc_top/dina<142>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>3" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>12" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dina<259>" COMP "u_sru_40dtc_top/dina<178>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_ack_0" COMP "u_sru_40dtc_top/addra<72>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dina<143>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dina<276>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/addra<76>" COMP "u_sru_40dtc_top/addra<79>" COMP "u_sru_40dtc_top/out_phase_cmd<10>" COMP "u_sru_40dtc_top/dina<139>" COMP "u_sru_40dtc_top/dina<135>" COMP "u_sru_40dtc_top/dina<149>" COMP "u_sru_40dtc_top/dina<285>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mcount_rd_frames_lut<0>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>1" COMP "u_sru_40dtc_top/dina<271>" COMP "u_sru_40dtc_top/addra<136>" COMP "u_sru_40dtc_top/dina<270>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_ack_0" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N4" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_13_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>3" COMP "u_sru_40dtc_top/dina<263>" COMP "u_sru_40dtc_top/dina<267>" COMP "u_sru_40dtc_top/dina<275>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_en" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dina<147>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_13_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "dtc_err_flag<4>" COMP "u_sru_40dtc_top/addra<132>" COMP "u_sru_40dtc_top/addra<140>" COMP "u_sru_40dtc_top/addra<143>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/addra<128>" COMP "u_sru_40dtc_top/dina<280>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/wea<5>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/wea<8>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<0>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N01" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/DtcRamFlag_i<5>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/DtcRamFlag_i<8>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<4>1" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "dtc_err_flag<8>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "errcnt<65>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "errcnt<81>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/_n0069" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<3>2" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3-In22" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "errcnt<64>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/N6" COMP "errcnt<77>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "errcnt<129>" COMP "errcnt<133>" COMP "errcnt<143>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<7>2" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/N01" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "errcnt<128>" COMP "errcnt<137>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<4>1" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<0>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_ack_0" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "errcnt<79>" COMP "errcnt<141>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "errcnt<69>" COMP "errcnt<85>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<7>2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3-In11" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "errcnt<80>" COMP "errcnt<73>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<4>2" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "errcnt<89>" COMP "errcnt<95>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "errcnt<93>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<0>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<1>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<7>2" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/N2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<0>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<5>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<2>2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>1" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In11" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<4>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In11" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In11" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/comp0" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp2" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp2" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/comp1" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>"; COMPGRP "dtc4_5_8.SLICE" LOCATE = SITE "SLICE_X56Y0:SLICE_X105Y39" LEVEL 4; COMPGRP dtc4_5_8.RAMB36 = COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"; COMPGRP "dtc4_5_8.RAMB36" LOCATE = SITE "RAMB36_X3Y0:RAMB36_X6Y7" LEVEL 4; COMPGRP dtc34_35.SLICE = COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<2>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<0>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<1>1" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<4>1" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/u_dtc_multiram/reset_a" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>3" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<4>2" COMP "u_sru_40dtc_top/dina<1131>" COMP "u_sru_40dtc_top/dina<1134>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dina<1123>" COMP "u_sru_40dtc_top/dina<1127>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dina<1138>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_13_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dina<1095>" COMP "errcnt<561>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "errcnt<545>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dina<1135>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dina<1141>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/N01" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_en" COMP "u_sru_40dtc_top/dina<1091>" COMP "u_sru_40dtc_top/dina<1102>" COMP "u_sru_40dtc_top/dina<1099>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>1" COMP "u_sru_40dtc_top/dina<1103>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dina<1149>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_cmd_par/dtc_out_phase_channel<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dina<1117>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In11" COMP "u_sru_cmd_par/Mmux_GND_76_o_GND_76_o_mux_366_OUT2934" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "dtc_err_flag<35>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dina<1107>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dina<1144>" COMP "u_sru_40dtc_top/dina<1139>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dina<1108>" COMP "u_sru_40dtc_top/dina<1140>" COMP "dtc_err_flag<34>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dina<1106>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dina<1109>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<2>2" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/DtcRamFlag_i<34>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en" COMP "u_sru_40dtc_top/addra<544>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "errcnt<544>" COMP "errcnt<549>" COMP "errcnt<557>" COMP "errcnt<559>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<2>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "errcnt<569>" COMP "errcnt<575>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/addra<560>" COMP "errcnt<553>" COMP "errcnt<560>" COMP "errcnt<565>" COMP "errcnt<573>" COMP "u_sru_40dtc_top/addra<552>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>2" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/addra<564>" COMP "u_sru_40dtc_top/addra<568>" COMP "u_sru_40dtc_top/addra<572>" COMP "u_sru_40dtc_top/addra<575>" COMP "u_sru_40dtc_top/wea<34>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/addra<559>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/addra<548>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<2>" COMP "u_sru_40dtc_top/addra<556>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp2" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>"; COMPGRP "dtc34_35.SLICE" LOCATE = SITE "SLICE_X0Y80:SLICE_X43Y119" LEVEL 4; COMPGRP dtc34_35.RAMB36 = COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"; COMPGRP "dtc34_35.RAMB36" LOCATE = SITE "RAMB36_X0Y16:RAMB36_X2Y23" LEVEL 4; COMPGRP dtc31_36_37_38_39.SLICE = COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/reset_rd" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<1>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<6>2" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<2>2" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/_n0069" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<7>2" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<0>1" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3-In11" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<1>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<5>1" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<3>2" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/_n0069" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<3>2" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<3>2" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/reset_40" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N4" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_en" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/N6" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<2>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>3" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_13_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<0>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N2" COMP "u_sru_40dtc_top/dina<1199>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dina<1195>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>2" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dina<1198>" COMP "u_sru_40dtc_top/dina<1187>" COMP "u_sru_40dtc_top/dina<1163>" COMP "u_sru_40dtc_top/dina<1223>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dina<1155>" COMP "u_sru_40dtc_top/dina<1003>" COMP "u_sru_40dtc_top/dina<1007>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dina<1191>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3-In11" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/rdocmd_i<39>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dina<1208>" COMP "u_sru_40dtc_top/dina<1166>" COMP "u_sru_40dtc_top/dina<1159>" COMP "u_sru_40dtc_top/dina<1230>" COMP "u_sru_40dtc_top/dina<1227>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>2" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dina<1245>" COMP "u_sru_40dtc_top/dina<1167>" COMP "u_sru_40dtc_top/dina<1173>" COMP "u_sru_40dtc_top/dina<1219>" COMP "u_sru_40dtc_top/dina<1205>" COMP "u_sru_40dtc_top/dina<1231>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dina<1181>" COMP "u_sru_40dtc_top/dina<1172>" COMP "errcnt<497>" COMP "u_sru_40dtc_top/dina<1204>" COMP "u_sru_40dtc_top/dina<1269>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/N6" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dina<1203>" COMP "u_sru_40dtc_top/dina<1213>" COMP "u_sru_40dtc_top/dina<1236>" COMP "u_sru_40dtc_top/dina<999>" COMP "u_sru_40dtc_top/dina<1176>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N4" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "dtc_err_flag<31>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus2<1>_inv" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<5>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<4>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dina<1171>" COMP "u_sru_40dtc_top/dina<1006>" COMP "u_sru_40dtc_top/dina<1240>" COMP "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dina<1234>" COMP "u_sru_40dtc_top/dina<1012>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "errcnt<593>" COMP "errcnt<609>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "dtc_err_flag<37>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "dtc_err_flag<38>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dina<995>" COMP "u_sru_40dtc_top/wea<36>" COMP "u_sru_40dtc_top/wea<38>" COMP "u_sru_40dtc_top/dina<1263>" COMP "errcnt<577>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>2" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<1>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dina<1021>" COMP "u_sru_40dtc_top/abortcmd_i<38>" COMP "u_sru_40dtc_top/addra<608>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<1>1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<0>1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dina<1013>" COMP "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dina<1262>" COMP "errcnt<505>" COMP "errcnt<625>" COMP "u_sru_40dtc_top/dina<1251>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "dtc_err_flag<39>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/reset_serbitclkdiv" COMP "u_sru_40dtc_top/dina<1267>" COMP "u_sru_40dtc_top/wea<31>" COMP "u_sru_40dtc_top/dina<1259>" COMP "u_sru_40dtc_top/dina<1255>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<2>1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dina<1266>" COMP "errcnt<501>" COMP "u_sru_40dtc_top/addra<496>" COMP "errcnt<509>" COMP "errcnt<511>" COMP "u_sru_40dtc_top/dina<1268>" COMP "u_sru_40dtc_top/addra<624>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/wea<39>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/DtcRamFlag_i<31>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dina<1272>" COMP "u_sru_40dtc_top/dina<1237>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "errcnt<592>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<7>2" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dina<1010>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/wea<37>" COMP "errcnt<581>" COMP "errcnt<585>" COMP "errcnt<639>" COMP "errcnt<589>" COMP "u_sru_40dtc_top/addra<604>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mcount_rd_frames_lut<0>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_reload_inv" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dina<1016>" COMP "u_sru_40dtc_top/addra<576>" COMP "u_sru_40dtc_top/addra<591>" COMP "u_sru_40dtc_top/addra<592>" COMP "errcnt<633>" COMP "u_sru_40dtc_top/addra<596>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/addra<623>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "errcnt<608>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/DtcRamFlag_i<36>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3-In2" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<1>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/addra<500>" COMP "u_sru_40dtc_top/addra<628>" COMP "u_sru_40dtc_top/addra<632>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/addra<616>" COMP "errcnt<637>" COMP "errcnt<591>" COMP "errcnt<576>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "errcnt<496>" COMP "u_sru_40dtc_top/addra<504>" COMP "u_sru_40dtc_top/addra<508>" COMP "u_sru_40dtc_top/addra<511>" COMP "u_sru_40dtc_top/addra<612>" COMP "u_sru_40dtc_top/addra<620>" COMP "errcnt<624>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/_n0343_inv" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<1>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/N2" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dina<1011>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/addra<639>" COMP "u_sru_40dtc_top/addra<636>" COMP "event_number<76>" COMP "u_sru_40dtc_top/addra<607>" COMP "event_number<84>" COMP "errcnt<597>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<10>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dina<1277>" COMP "errcnt<629>" COMP "event_number<48>" COMP "u_sru_40dtc_top/addra<600>" COMP "errcnt<601>" COMP "errcnt<605>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_reload_inv" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3-In11" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/addra<584>" COMP "u_sru_40dtc_top/addra<588>" COMP "event_number<40>" COMP "event_number<64>" COMP "event_number<72>" COMP "errcnt<623>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/addra<580>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "errcnt<613>" COMP "errcnt<617>" COMP "errcnt<621>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/comp0" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/comp1" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>"; COMPGRP "dtc31_36_37_38_39.SLICE" LOCATE = SITE "SLICE_X0Y120:SLICE_X43Y159" LEVEL 4; COMPGRP dtc31_36_37_38_39.RAMB36 = COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"; COMPGRP "dtc31_36_37_38_39.RAMB36" LOCATE = SITE "RAMB36_X0Y24:RAMB36_X2Y31" LEVEL 4; COMPGRP dtc24_32_33.SLICE = COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_cmd_par/Mmux_GND_76_o_GND_76_o_mux_366_OUT26" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3-In11" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/_n0069" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_13_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In11" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "N6" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dina<1067>" COMP "u_sru_40dtc_top/dina<1059>" COMP "u_sru_40dtc_top/dina<1071>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dina<1075>" COMP "u_sru_40dtc_top/dina<1063>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dina<1077>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/N2" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg<172>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<0>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dina<1070>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "errcnt<529>" COMP "u_sru_40dtc_top/dina<1031>" COMP "u_sru_40dtc_top/dina<1035>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dina<1027>" COMP "errcnt<513>" COMP "u_sru_40dtc_top/dina<1053>" COMP "u_sru_40dtc_top/dina<1039>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dina<1038>" COMP "u_sru_40dtc_top/dina<1043>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dina<1085>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dina<1048>" COMP "u_sru_40dtc_top/dina<1074>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "dtc_deser_dout<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dina<1045>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dina<1080>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "dtc_err_flag<33>" COMP "u_sru_40dtc_top/dina<1044>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_addr<3>" COMP "errcnt<385>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt<4>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_data<7>" COMP "errcnt<397>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dina<1076>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus2<1>_inv" COMP "u_sru_40dtc_top/dina<1042>" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/reset_serbitclkdiv" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/reset_serbitclkdiv" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/reset_serbitclkdiv" COMP "errcnt<393>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "dtc_err_flag<32>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>" COMP "errcnt<389>" COMP "errcnt<384>" COMP "errcnt<399>" COMP "dtc_err_flag<24>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In13" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "dtc_deser_dout<5>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd3-In2" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/wea<33>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "errcnt<533>" COMP "errcnt<512>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/addra<528>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "errcnt<537>" COMP "errcnt<521>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/wea<32>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<7>" COMP "u_sru_40dtc_top/dina<775>" COMP "u_sru_40dtc_top/wea<24>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/addra<512>" COMP "errcnt<525>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<10>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<10>" COMP "u_sru_40dtc_top/addra<520>" COMP "u_sru_40dtc_top/addra<524>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/DtcRamFlag_i<32>" COMP "errcnt<517>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<2>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<5>" COMP "u_sru_40dtc_top/addra<516>" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_ram_dina_1168" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "errcnt<528>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "errcnt<526>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<6>" COMP "errcnt<541>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/addra<536>" COMP "u_sru_40dtc_top/addra<532>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<9>" COMP "u_sru_40dtc_top/addra<540>" COMP "u_sru_40dtc_top/dina<782>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>2" COMP "u_sru_40dtc_top/dina<771>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>12" COMP "u_sru_40dtc_top/addra<384>" COMP "u_sru_40dtc_top/dina<786>" COMP "u_sru_40dtc_top/DtcRamFlag_i<24>" COMP "u_sru_40dtc_top/dina<779>" COMP "u_sru_40dtc_top/addra<388>" COMP "u_sru_40dtc_top/dina<792>" COMP "u_sru_40dtc_top/dina<783>" COMP "u_sru_40dtc_top/addra<392>" COMP "u_sru_40dtc_top/addra<396>" COMP "u_sru_40dtc_top/addra<399>" COMP "u_sru_40dtc_top/dina<797>" COMP "u_sru_40dtc_top/dina<789>" COMP "u_sru_40dtc_top/dina<788>" COMP "u_sru_40dtc_top/dina<787>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp2" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp2" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>"; COMPGRP "dtc24_32_33.SLICE" LOCATE = SITE "SLICE_X0Y99:SLICE_X55Y60" LEVEL 4; COMPGRP dtc24_32_33.RAMB36 = COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"; COMPGRP "dtc24_32_33.RAMB36" LOCATE = SITE "RAMB36_X0Y12:RAMB36_X2Y19" LEVEL 4; COMPGRP dtc1_2.SLICE = COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_rd" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/reset_bitclkdiv" COMP "u_sru_40dtc_top/dina<53>" COMP "u_sru_40dtc_top/dina<50>" COMP "u_sru_40dtc_top/dina<61>" COMP "u_sru_40dtc_top/dina<56>" COMP "u_sru_40dtc_top/dina<51>" COMP "u_sru_40dtc_top/dina<82>" COMP "u_sru_40dtc_top/dina<93>" COMP "u_sru_40dtc_top/dina<39>" COMP "errcnt<37>" COMP "u_sru_40dtc_top/addra<24>" COMP "u_sru_40dtc_top/addra<28>" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_index_1[5]_X_713_o_Mux_10_o_102" COMP "u_sru_40dtc_top/dina<43>" COMP "u_sru_40dtc_top/dina<46>" COMP "errcnt<41>" COMP "errcnt<45>" COMP "errcnt<47>" COMP "u_sru_40dtc_top/addra<20>" COMP "u_sru_40dtc_top/addra<31>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N2" COMP "u_sru_40dtc_top/dina<47>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>" COMP "u_sru_40dtc_top/addra<16>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>12" COMP "u_sru_40dtc_top/dina<67>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N4" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dina<52>" COMP "u_sru_40dtc_top/dina<78>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dina<35>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/wea<1>" COMP "u_sru_40dtc_top/dina<71>" COMP "u_sru_40dtc_top/dina<79>" COMP "u_sru_40dtc_top/dina<84>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "errcnt<33>" COMP "errcnt<32>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dina<85>" COMP "u_sru_40dtc_top/dina<83>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_ram_wr_addr_171" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>3" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dina<88>" COMP "errcnt<17>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>3" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dina<75>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/DtcRamFlag_i<1>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "errcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/addra<32>" COMP "errcnt<21>" COMP "errcnt<25>" COMP "errcnt<29>" COMP "u_sru_40dtc_top/wea<2>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "dtc_err_flag<2>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/DtcRamFlag_i<2>" COMP "u_sru_40dtc_top/addra<36>" COMP "errcnt<31>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "dtc_err_flag<1>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/addra<40>" COMP "u_sru_40dtc_top/addra<44>" COMP "u_sru_40dtc_top/addra<47>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<5>1" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<5>1" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mcount_rd_frames_lut<0>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In13" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_en" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3-In11" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>2" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/_n0069" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<4>1" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<1>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<5>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/rdocmd_i<2>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_ack_0" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<0>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<5>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<1>1" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<2>1" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<2>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3-In11" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>1" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/_n0069" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<1>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/comp0" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3-In2" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<4>1" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_ack_0" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>"; COMPGRP "dtc1_2.SLICE" LOCATE = SITE "SLICE_X56Y60:SLICE_X105Y99" LEVEL 4; COMPGRP dtc18_19_27_29.SLICE = COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_rd" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<5>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<4>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<1>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_reload_inv" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_13_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dina<942>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dina<935>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" COMP "u_sru_40dtc_top/dina<867>" COMP "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dina<943>" COMP "u_sru_40dtc_top/dina<931>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dina<878>" COMP "u_sru_40dtc_top/dina<875>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dina<939>" COMP "u_sru_40dtc_top/dina<879>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "errcnt<433>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<1>" COMP "dtc_err_flag<29>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/rdocmd_i<21>" COMP "u_sru_40dtc_top/dina<871>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "errcnt<465>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dina<946>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<1>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/reset_40" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dina<893>" COMP "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "dtc_err_flag<27>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>2" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dina<957>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dina<952>" COMP "u_sru_40dtc_top/dina<948>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dina<882>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/DtcRamFlag_i<18>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dina<883>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<4>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dina<629>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/wea<18>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "errcnt<288>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/DtcRamFlag_i<27>" COMP "u_sru_40dtc_top/dina<619>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/wea<27>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/addra<432>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "errcnt<437>" COMP "errcnt<441>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/DtcRamFlag_i<19>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "errcnt<447>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<1>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_cmd_par/Mmux_GND_76_o_GND_76_o_mux_366_OUT2630" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "errcnt<432>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dina<949>" COMP "u_sru_40dtc_top/dina<632>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dina<615>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dina<623>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/DtcRamFlag_i<29>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "errcnt<445>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dina<626>" COMP "u_sru_40dtc_top/dina<611>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<5>" COMP "errcnt<477>" COMP "errcnt<469>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/wea<29>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dina<628>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dina<622>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dina<637>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/u_dtc_multiram/ram_dina_0<30>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "errcnt<304>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dina<947>" COMP "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/addra<288>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "errcnt<309>" COMP "errcnt<313>" COMP "u_sru_40dtc_top/addra<447>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "dtc_err_flag<19>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/addra<464>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dina<579>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "errcnt<305>" COMP "errcnt<317>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "errcnt<301>" COMP "u_sru_40dtc_top/addra<440>" COMP "errcnt<473>" COMP "dtc_err_flag<18>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/addra<472>" COMP "u_sru_40dtc_top/dina<590>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_13_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "errcnt<289>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "errcnt<293>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/addra<468>" COMP "u_sru_40dtc_top/dina<595>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "errcnt<297>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "errcnt<464>" COMP "errcnt<479>" COMP "u_sru_40dtc_top/dina<587>" COMP "u_sru_40dtc_top/dina<583>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/addra<436>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/addra<476>" COMP "u_sru_40dtc_top/addra<479>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dina<597>" COMP "u_sru_40dtc_top/dina<591>" COMP "u_sru_40dtc_top/addra<292>" COMP "u_sru_40dtc_top/addra<296>" COMP "u_sru_40dtc_top/addra<300>" COMP "u_sru_cmd_par/Mmux_GND_76_o_GND_76_o_mux_366_OUT3159" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/addra<444>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dina<605>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/addra<303>" COMP "errcnt<303>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dina<600>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dina<596>" COMP "u_sru_40dtc_top/dina<594>" COMP "u_sru_40dtc_top/addra<304>" COMP "u_sru_40dtc_top/addra<308>" COMP "u_sru_40dtc_top/addra<312>" COMP "u_sru_40dtc_top/addra<316>" COMP "u_sru_40dtc_top/addra<319>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>"; COMPGRP "dtc18_19_27_29.SLICE" LOCATE = SITE "SLICE_X0Y40:SLICE_X55Y79" LEVEL 4; COMPGRP dtc18_19_27_29.RAMB36 = COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"; COMPGRP "dtc18_19_27_29.RAMB36" LOCATE = SITE "RAMB36_X0Y8:RAMB36_X2Y15" LEVEL 4; COMPGRP dtc11_12_13_14_20_21_22_25.SLICE = COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_rd" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_rd" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_rd" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_wr" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/reset_40" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<5>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_reload_inv" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/N01" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<1>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<10>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<0>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt<4>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/_n0069" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dina<679>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "errcnt<353>" COMP "u_sru_40dtc_top/dina<675>" COMP "u_sru_40dtc_top/dina<683>" COMP "u_sru_40dtc_top/dina<819>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "dtc_err_flag<21>" COMP "u_sru_40dtc_top/dina<687>" COMP "u_sru_40dtc_top/dina<686>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dina<814>" COMP "u_sru_40dtc_top/dina<707>" COMP "u_sru_40dtc_top/dina<690>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<1>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/rdocmd_i<22>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dina<701>" COMP "u_sru_40dtc_top/dina<815>" COMP "u_sru_40dtc_top/dina<807>" COMP "u_sru_40dtc_top/dina<696>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "errcnt<401>" COMP "errcnt<321>" COMP "u_sru_40dtc_top/dina<643>" COMP "u_sru_40dtc_top/dina<711>" COMP "u_sru_40dtc_top/dina<803>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "dtc_err_flag<20>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dina<811>" COMP "u_sru_40dtc_top/dina<718>" COMP "u_sru_40dtc_top/dina<715>" COMP "u_sru_40dtc_top/dina<691>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/rdocmd_i<17>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dina<829>" COMP "u_sru_40dtc_top/dina<733>" COMP "errcnt<349>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/reset_serbitclkdiv" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "errcnt<336>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "errcnt<400>" COMP "errcnt<361>" COMP "errcnt<405>" COMP "errcnt<409>" COMP "errcnt<413>" COMP "u_sru_40dtc_top/dina<820>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/wea<20>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dina<654>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dina<719>" COMP "errcnt<365>" COMP "u_sru_40dtc_top/dina<664>" COMP "errcnt<415>" COMP "u_sru_40dtc_top/dina<659>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "errcnt<352>" COMP "u_sru_40dtc_top/dina<651>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dina<669>" COMP "u_sru_40dtc_top/dina<434>" COMP "u_sru_40dtc_top/dina<722>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dina<427>" COMP "u_sru_40dtc_top/DtcRamFlag_i<25>" COMP "u_sru_40dtc_top/dina<647>" COMP "errcnt<357>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dina<373>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dina<440>" COMP "u_sru_40dtc_top/wea<25>" COMP "errcnt<341>" COMP "u_sru_40dtc_top/dina<728>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dina<430>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dina<445>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "errcnt<176>" COMP "u_sru_40dtc_top/dina<451>" COMP "u_sru_40dtc_top/dina<387>" COMP "errcnt<345>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dina<419>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dina<366>" COMP "u_sru_40dtc_top/addra<336>" COMP "u_sru_40dtc_top/dina<398>" COMP "u_sru_40dtc_top/dina<376>" COMP "u_sru_40dtc_top/dina<363>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dina<423>" COMP "u_sru_40dtc_top/wea<22>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dina<463>" COMP "u_sru_40dtc_top/dina<395>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dina<391>" COMP "u_sru_40dtc_top/dina<723>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In11" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dina<431>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dina<359>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>" COMP "u_sru_40dtc_top/dina<459>" COMP "errcnt<367>" COMP "u_sru_40dtc_top/dina<399>" COMP "u_sru_40dtc_top/dina<660>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "dtc_err_flag<12>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/addra<176>" COMP "u_sru_40dtc_top/dina<355>" COMP "u_sru_40dtc_top/addra<408>" COMP "errcnt<239>" COMP "u_sru_40dtc_top/dina<466>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<2>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/addra<320>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dina<367>" COMP "u_sru_40dtc_top/dina<455>" COMP "errcnt<197>" COMP "u_sru_40dtc_top/addra<400>" COMP "errcnt<320>" COMP "u_sru_40dtc_top/addra<415>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/addra<191>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" COMP "u_sru_40dtc_top/dina<371>" COMP "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<0>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In11" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/DtcRamFlag_i<14>" COMP "u_sru_40dtc_top/dina<468>" COMP "u_sru_40dtc_top/dina<408>" COMP "errcnt<325>" COMP "errcnt<329>" COMP "errcnt<333>" COMP "u_sru_40dtc_top/dina<372>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In13" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "errcnt<224>" COMP "u_sru_40dtc_top/addra<224>" COMP "errcnt<191>" COMP "u_sru_40dtc_top/addra<344>" COMP "u_sru_40dtc_top/dina<477>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/wea<13>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/addra<180>" COMP "errcnt<185>" COMP "u_sru_40dtc_top/addra<228>" COMP "u_sru_40dtc_top/addra<220>" COMP "u_sru_40dtc_top/addra<236>" COMP "u_sru_40dtc_top/addra<188>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In11" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/N6" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/addra<192>" COMP "u_sru_40dtc_top/addra<207>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/addra<212>" COMP "u_sru_40dtc_top/addra<348>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dina<413>" COMP "u_sru_40dtc_top/addra<216>" COMP "u_sru_40dtc_top/dina<404>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg<172>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3-In11" COMP "u_sru_40dtc_top/addra<200>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "errcnt<209>" COMP "u_sru_40dtc_top/dina<437>" COMP "u_sru_40dtc_top/addra<340>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dina<435>" COMP "u_sru_40dtc_top/dina<381>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<0>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "dtc_err_flag<13>" COMP "u_sru_40dtc_top/addra<239>" COMP "u_sru_40dtc_top/addra<328>" COMP "u_sru_40dtc_top/addra<332>" COMP "errcnt<213>" COMP "errcnt<223>" COMP "u_sru_40dtc_top/addra<404>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "errcnt<177>" COMP "u_sru_40dtc_top/addra<324>" COMP "u_sru_40dtc_top/addra<367>" COMP "u_sru_40dtc_top/addra<335>" COMP "u_sru_40dtc_top/addra<232>" COMP "errcnt<217>" COMP "u_sru_40dtc_top/addra<412>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" COMP "u_sru_40dtc_top/dina<405>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In11" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dina<472>" COMP "errcnt<221>" COMP "errcnt<189>" COMP "u_sru_40dtc_top/dina<469>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "errcnt<207>" COMP "u_sru_40dtc_top/addra<356>" COMP "u_sru_40dtc_top/addra<360>" COMP "errcnt<237>" COMP "errcnt<181>" COMP "errcnt<205>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/addra<196>" COMP "u_sru_40dtc_top/addra<204>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "errcnt<233>" COMP "errcnt<201>" COMP "u_sru_40dtc_top/addra<364>" COMP "errcnt<229>" COMP "u_sru_40dtc_top/addra<184>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>"; COMPGRP "dtc11_12_13_14_20_21_22_25.SLICE" LOCATE = SITE "SLICE_X0Y0:SLICE_X55Y39" LEVEL 4; COMPGRP dtc11_12_13_14_20_21_22_25.RAMB36 = COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"; COMPGRP "dtc11_12_13_14_20_21_22_25.RAMB36" LOCATE = SITE "RAMB36_X0Y0:RAMB36_X2Y7" LEVEL 4; COMPGRP dtc0_3_7.SLICE = COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/reset_wr" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<1>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/reset_40" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/reset_40" COMP "u_sru_40dtc_top/dina<114>" COMP "u_sru_40dtc_top/dina<107>" COMP "u_sru_40dtc_top/dina<111>" COMP "u_sru_cmd_par/Mmux_GND_76_o_GND_76_o_mux_366_OUT3156" COMP "u_sru_40dtc_top/dina<245>" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_ram_wr_addr_11411" COMP "u_sru_40dtc_top/dina<242>" COMP "u_sru_40dtc_top/dina<117>" COMP "u_sru_40dtc_top/dina<116>" COMP "u_sru_40dtc_top/dina<125>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>12" COMP "u_sru_40dtc_top/dina<110>" COMP "u_sru_40dtc_top/dina<103>" COMP "errcnt<49>" COMP "u_sru_40dtc_top/dina<253>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>3" COMP "u_sru_40dtc_top/dina<18>" COMP "u_sru_40dtc_top/dina<248>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dina<115>" COMP "u_sru_cmd_par/Mmux_GND_76_o_GND_76_o_mux_366_OUT245" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_ack_0" COMP "u_sru_40dtc_top/dina<243>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>12" COMP "u_sru_40dtc_top/dina<29>" COMP "u_sru_40dtc_top/dina<21>" COMP "u_sru_40dtc_top/dina<244>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>11" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_ram_dina_12515" COMP "u_sru_40dtc_top/dina<14>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dina<227>" COMP "u_sru_40dtc_top/dina<235>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N4" COMP "errcnt<48>" COMP "u_sru_40dtc_top/dina<231>" COMP "errcnt<53>" COMP "errcnt<57>" COMP "errcnt<63>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>12" COMP "u_sru_40dtc_top/dina<120>" COMP "u_sru_40dtc_top/dina<99>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_13_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dina<239>" COMP "u_sru_40dtc_top/dina<238>" COMP "u_sru_40dtc_top/addra<63>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_ram_wr_addr_044" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>3" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/addra<52>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>1" COMP "u_sru_40dtc_top/dina<24>" COMP "u_sru_40dtc_top/dina<19>" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_ram_wr_addr_0102" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/addra<56>" COMP "u_sru_40dtc_top/addra<60>" COMP "errcnt<61>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_sof_n_i" COMP "u_sru_40dtc_top/dina<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dina<7>" COMP "u_sru_40dtc_top/addra<48>" COMP "u_sru_40dtc_top/wea<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_46_ML_NEW_I0" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_en" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dina<15>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dina<20>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/addra<116>" COMP "u_sru_40dtc_top/addra<120>" COMP "u_sru_40dtc_top/addra<124>" COMP "u_sru_40dtc_top/addra<127>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_src_rdy_n_i" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_13_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>3" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>2" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/addra<4>" COMP "u_sru_40dtc_top/addra<8>" COMP "u_sru_40dtc_top/dina<3>" COMP "u_sru_40dtc_top/wea<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/u_dtc_multiram/Mmux_ram_wr_addr_022" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N01" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_11_o<15>1" COMP "u_sru_40dtc_top/addra<112>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/addra<12>" COMP "u_sru_40dtc_top/addra<15>" COMP "u_sru_40dtc_top/addra<0>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dtc_deser_dout[15]_PWR_76_o_equal_13_o<15>1" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/wea<0>" COMP "dtc_err_flag<0>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/_n0069" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/N4" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_eof_n_i" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<0>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/DtcRamFlag_i<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3-In11" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<3>2" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" COMP "errcnt<113>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<27>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "errcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_rd_pull_frame_AND_97_o_inv" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_update" COMP "errcnt<5>" COMP "errcnt<9>" COMP "errcnt<0>" COMP "errcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_en" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>2" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_reload" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<5>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<10>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<23>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<7>" COMP "errcnt<13>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>1" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3-In2" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<1>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<19>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<15>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In13" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_cmd_par/udp_cmd_addr[15]_GND_76_o_equal_297_o<15>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<43>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<31>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt<0>" COMP "errcnt<112>" COMP "errcnt<117>" COMP "errcnt<125>" COMP "errcnt<127>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<35>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<0>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<0>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/FastCmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "errcnt<121>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<2>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<1>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In11" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<6>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus2<1>_inv" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr<1>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1-In13" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<51>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe<2>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_ack_0" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<39>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<6>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st[4]_GND_104_o_select_24_OUT<5>1" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/abortcmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<59>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<55>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/N01" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_sdout" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<47>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<6>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<5>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<6>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<4>1" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_dv_ack" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt<2>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/rdocmd_buffer" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/dcs_cmd_reply<63>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>2" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<0>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<6>2" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wr_pntr_plus2<1>_inv" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg<1>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<8>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<9>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>1" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/D<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<5>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin<1>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_data<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<6>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<1>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_addr<27>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<5>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<0>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg<2>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<9>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<8>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_data<31>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_data<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_data<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3-In11" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<5>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<9>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<6>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<5>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2<9>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_data<27>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_data<19>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_empty" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<1>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<8>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<3>1" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<8>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<4>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<0>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg<5>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin<2>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<8>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_data<23>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_addr<19>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/_n0069" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/N01" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<9>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_addr<31>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c0/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_addr<23>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<5>2" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_st[14]_GND_124_o_select_20_OUT<2>2" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c2/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp2" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_addr<15>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/udp_cmd_data<15>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<15>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt<16>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/Madd_addra[15]_GND_109_o_add_11_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra[15]_GND_109_o_add_11_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Madd_errcnt[15]_GND_104_o_add_39_OUT_cy<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt[15]_GND_104_o_add_39_OUT<15>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/c1/gmux.carrynet<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<7>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr<11>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/rd_data_out_i<4>" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram<3>"; COMPGRP "dtc0_3_7.SLICE" LOCATE = SITE "SLICE_X56Y40:SLICE_X105Y79" LEVEL 4; COMPGRP dtc0_3_7.RAMB36 = COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" COMP "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" COMP "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram"; COMPGRP "dtc0_3_7.RAMB36" LOCATE = SITE "RAMB36_X3Y8:RAMB36_X6Y15" LEVEL 4; PIN u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<3> = BEL "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst" PINNAME CLKIN2; TIMEGRP u_main_clk_gen_UTLUSyncPLL_clkout0 = BEL "htrig_number_d" BEL "htrig_d" BEL "sru_trig_synced_out_nim" BEL "u_main_clk_gen/TrigIOClkSel" BEL "u_main_clk_gen/UTLUSyncPLL/clkout1_buf" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<3>"; TIMEGRP u_main_clk_gen_UTLUSyncPLL_clkout0_0 = BEL "htrig_number_d" BEL "htrig_d" BEL "sru_trig_synced_out_nim" BEL "u_main_clk_gen/TrigIOClkSel" BEL "u_main_clk_gen/UTLUSyncPLL/clkout1_buf" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<3>"; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT" PINNAME CK; PIN u_sru_cmd_par/u_srutempmonitor/SYSMON_INST_pins<10> = BEL "u_sru_cmd_par/u_srutempmonitor/SYSMON_INST" PINNAME DCLK; PIN u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33> = BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<65> = BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<64> = BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout3 = BEL "htrig_number_d" BEL "spill_sync_dd" BEL "u_sru_40dtc_top/DtcRamFlag_ii_39" BEL "u_sru_40dtc_top/DtcRamFlag_ii_38" BEL "u_sru_40dtc_top/DtcRamFlag_ii_37" BEL "u_sru_40dtc_top/DtcRamFlag_ii_36" BEL "u_sru_40dtc_top/DtcRamFlag_ii_35" BEL "u_sru_40dtc_top/DtcRamFlag_ii_34" BEL "u_sru_40dtc_top/DtcRamFlag_ii_33" BEL "u_sru_40dtc_top/DtcRamFlag_ii_32" BEL "u_sru_40dtc_top/DtcRamFlag_ii_31" BEL "u_sru_40dtc_top/DtcRamFlag_ii_30" BEL "u_sru_40dtc_top/DtcRamFlag_ii_29" BEL "u_sru_40dtc_top/DtcRamFlag_ii_28" BEL "u_sru_40dtc_top/DtcRamFlag_ii_27" BEL "u_sru_40dtc_top/DtcRamFlag_ii_26" BEL "u_sru_40dtc_top/DtcRamFlag_ii_25" BEL "u_sru_40dtc_top/DtcRamFlag_ii_24" BEL "u_sru_40dtc_top/DtcRamFlag_ii_23" BEL "u_sru_40dtc_top/DtcRamFlag_ii_22" BEL "u_sru_40dtc_top/DtcRamFlag_ii_21" BEL "u_sru_40dtc_top/DtcRamFlag_ii_20" BEL "u_sru_40dtc_top/DtcRamFlag_ii_19" BEL "u_sru_40dtc_top/DtcRamFlag_ii_18" BEL "u_sru_40dtc_top/DtcRamFlag_ii_17" BEL "u_sru_40dtc_top/DtcRamFlag_ii_16" BEL "u_sru_40dtc_top/DtcRamFlag_ii_15" BEL "u_sru_40dtc_top/DtcRamFlag_ii_14" BEL "u_sru_40dtc_top/DtcRamFlag_ii_13" BEL "u_sru_40dtc_top/DtcRamFlag_ii_12" BEL "u_sru_40dtc_top/DtcRamFlag_ii_11" BEL "u_sru_40dtc_top/DtcRamFlag_ii_10" BEL "u_sru_40dtc_top/DtcRamFlag_ii_9" BEL "u_sru_40dtc_top/DtcRamFlag_ii_8" BEL "u_sru_40dtc_top/DtcRamFlag_ii_7" BEL "u_sru_40dtc_top/DtcRamFlag_ii_6" BEL "u_sru_40dtc_top/DtcRamFlag_ii_5" BEL "u_sru_40dtc_top/DtcRamFlag_ii_4" BEL "u_sru_40dtc_top/DtcRamFlag_ii_3" BEL "u_sru_40dtc_top/DtcRamFlag_ii_2" BEL "u_sru_40dtc_top/DtcRamFlag_ii_1" BEL "u_sru_40dtc_top/DtcRamFlag_ii_0" BEL "u_sru_40dtc_top/abortcmd_i_39" BEL "u_sru_40dtc_top/abortcmd_i_38" BEL "u_sru_40dtc_top/abortcmd_i_37" BEL "u_sru_40dtc_top/abortcmd_i_36" BEL "u_sru_40dtc_top/abortcmd_i_35" BEL "u_sru_40dtc_top/abortcmd_i_34" BEL "u_sru_40dtc_top/abortcmd_i_33" BEL "u_sru_40dtc_top/abortcmd_i_32" BEL "u_sru_40dtc_top/abortcmd_i_31" BEL "u_sru_40dtc_top/abortcmd_i_30" BEL "u_sru_40dtc_top/abortcmd_i_29" BEL "u_sru_40dtc_top/abortcmd_i_28" BEL "u_sru_40dtc_top/abortcmd_i_27" BEL "u_sru_40dtc_top/abortcmd_i_26" BEL "u_sru_40dtc_top/abortcmd_i_25" BEL "u_sru_40dtc_top/abortcmd_i_24" BEL "u_sru_40dtc_top/abortcmd_i_23" BEL "u_sru_40dtc_top/abortcmd_i_22" BEL "u_sru_40dtc_top/abortcmd_i_21" BEL "u_sru_40dtc_top/abortcmd_i_20" BEL "u_sru_40dtc_top/abortcmd_i_19" BEL "u_sru_40dtc_top/abortcmd_i_18" BEL "u_sru_40dtc_top/abortcmd_i_17" BEL "u_sru_40dtc_top/abortcmd_i_16" BEL "u_sru_40dtc_top/abortcmd_i_15" BEL "u_sru_40dtc_top/abortcmd_i_14" BEL "u_sru_40dtc_top/abortcmd_i_13" BEL "u_sru_40dtc_top/abortcmd_i_12" BEL "u_sru_40dtc_top/abortcmd_i_11" BEL "u_sru_40dtc_top/abortcmd_i_10" BEL "u_sru_40dtc_top/abortcmd_i_9" BEL "u_sru_40dtc_top/abortcmd_i_8" BEL "u_sru_40dtc_top/abortcmd_i_7" BEL "u_sru_40dtc_top/abortcmd_i_6" BEL "u_sru_40dtc_top/abortcmd_i_5" BEL "u_sru_40dtc_top/abortcmd_i_4" BEL "u_sru_40dtc_top/abortcmd_i_3" BEL "u_sru_40dtc_top/abortcmd_i_2" BEL "u_sru_40dtc_top/abortcmd_i_1" BEL "u_sru_40dtc_top/abortcmd_i_0" BEL "u_sru_40dtc_top/DTCEventRdy_i_39" BEL "u_sru_40dtc_top/DTCEventRdy_i_38" BEL "u_sru_40dtc_top/DTCEventRdy_i_37" BEL "u_sru_40dtc_top/DTCEventRdy_i_36" BEL "u_sru_40dtc_top/DTCEventRdy_i_35" BEL "u_sru_40dtc_top/DTCEventRdy_i_34" BEL "u_sru_40dtc_top/DTCEventRdy_i_33" BEL "u_sru_40dtc_top/DTCEventRdy_i_32" BEL "u_sru_40dtc_top/DTCEventRdy_i_31" BEL "u_sru_40dtc_top/DTCEventRdy_i_30" BEL "u_sru_40dtc_top/DTCEventRdy_i_29" BEL "u_sru_40dtc_top/DTCEventRdy_i_28" BEL "u_sru_40dtc_top/DTCEventRdy_i_27" BEL "u_sru_40dtc_top/DTCEventRdy_i_26" BEL "u_sru_40dtc_top/DTCEventRdy_i_25" BEL "u_sru_40dtc_top/DTCEventRdy_i_24" BEL "u_sru_40dtc_top/DTCEventRdy_i_23" BEL "u_sru_40dtc_top/DTCEventRdy_i_22" BEL "u_sru_40dtc_top/DTCEventRdy_i_21" BEL "u_sru_40dtc_top/DTCEventRdy_i_20" BEL "u_sru_40dtc_top/DTCEventRdy_i_19" BEL "u_sru_40dtc_top/DTCEventRdy_i_18" BEL "u_sru_40dtc_top/DTCEventRdy_i_17" BEL "u_sru_40dtc_top/DTCEventRdy_i_16" BEL "u_sru_40dtc_top/DTCEventRdy_i_15" BEL "u_sru_40dtc_top/DTCEventRdy_i_14" BEL "u_sru_40dtc_top/DTCEventRdy_i_13" BEL "u_sru_40dtc_top/DTCEventRdy_i_12" BEL "u_sru_40dtc_top/DTCEventRdy_i_11" BEL "u_sru_40dtc_top/DTCEventRdy_i_10" BEL "u_sru_40dtc_top/DTCEventRdy_i_9" BEL "u_sru_40dtc_top/DTCEventRdy_i_8" BEL "u_sru_40dtc_top/DTCEventRdy_i_7" BEL "u_sru_40dtc_top/DTCEventRdy_i_6" BEL "u_sru_40dtc_top/DTCEventRdy_i_5" BEL "u_sru_40dtc_top/DTCEventRdy_i_4" BEL "u_sru_40dtc_top/DTCEventRdy_i_3" BEL "u_sru_40dtc_top/DTCEventRdy_i_2" BEL "u_sru_40dtc_top/DTCEventRdy_i_1" BEL "u_sru_40dtc_top/DTCEventRdy_i_0" BEL "u_sru_40dtc_top/FeeTrig_i_39" BEL "u_sru_40dtc_top/FeeTrig_i_38" BEL "u_sru_40dtc_top/FeeTrig_i_37" BEL "u_sru_40dtc_top/FeeTrig_i_36" BEL "u_sru_40dtc_top/FeeTrig_i_35" BEL "u_sru_40dtc_top/FeeTrig_i_34" BEL "u_sru_40dtc_top/FeeTrig_i_33" BEL "u_sru_40dtc_top/FeeTrig_i_32" BEL "u_sru_40dtc_top/FeeTrig_i_31" BEL "u_sru_40dtc_top/FeeTrig_i_30" BEL "u_sru_40dtc_top/FeeTrig_i_29" BEL "u_sru_40dtc_top/FeeTrig_i_28" BEL "u_sru_40dtc_top/FeeTrig_i_27" BEL "u_sru_40dtc_top/FeeTrig_i_26" BEL "u_sru_40dtc_top/FeeTrig_i_25" BEL "u_sru_40dtc_top/FeeTrig_i_24" BEL "u_sru_40dtc_top/FeeTrig_i_23" BEL "u_sru_40dtc_top/FeeTrig_i_22" BEL "u_sru_40dtc_top/FeeTrig_i_21" BEL "u_sru_40dtc_top/FeeTrig_i_20" BEL "u_sru_40dtc_top/FeeTrig_i_19" BEL "u_sru_40dtc_top/FeeTrig_i_18" BEL "u_sru_40dtc_top/FeeTrig_i_17" BEL "u_sru_40dtc_top/FeeTrig_i_16" BEL "u_sru_40dtc_top/FeeTrig_i_15" BEL "u_sru_40dtc_top/FeeTrig_i_14" BEL "u_sru_40dtc_top/FeeTrig_i_13" BEL "u_sru_40dtc_top/FeeTrig_i_12" BEL "u_sru_40dtc_top/FeeTrig_i_11" BEL "u_sru_40dtc_top/FeeTrig_i_10" BEL "u_sru_40dtc_top/FeeTrig_i_9" BEL "u_sru_40dtc_top/FeeTrig_i_8" BEL "u_sru_40dtc_top/FeeTrig_i_7" BEL "u_sru_40dtc_top/FeeTrig_i_6" BEL "u_sru_40dtc_top/FeeTrig_i_5" BEL "u_sru_40dtc_top/FeeTrig_i_4" BEL "u_sru_40dtc_top/FeeTrig_i_3" BEL "u_sru_40dtc_top/FeeTrig_i_2" BEL "u_sru_40dtc_top/FeeTrig_i_1" BEL "u_sru_40dtc_top/FeeTrig_i_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/clk_ODELAY" BEL "u_sru_cmd_par/BusyCnt_31" BEL "u_sru_cmd_par/BusyCnt_30" BEL "u_sru_cmd_par/BusyCnt_29" BEL "u_sru_cmd_par/BusyCnt_28" BEL "u_sru_cmd_par/BusyCnt_27" BEL "u_sru_cmd_par/BusyCnt_26" BEL "u_sru_cmd_par/BusyCnt_25" BEL "u_sru_cmd_par/BusyCnt_24" BEL "u_sru_cmd_par/BusyCnt_23" BEL "u_sru_cmd_par/BusyCnt_22" BEL "u_sru_cmd_par/BusyCnt_21" BEL "u_sru_cmd_par/BusyCnt_20" BEL "u_sru_cmd_par/BusyCnt_19" BEL "u_sru_cmd_par/BusyCnt_18" BEL "u_sru_cmd_par/BusyCnt_17" BEL "u_sru_cmd_par/BusyCnt_16" BEL "u_sru_cmd_par/BusyCnt_15" BEL "u_sru_cmd_par/BusyCnt_14" BEL "u_sru_cmd_par/BusyCnt_13" BEL "u_sru_cmd_par/BusyCnt_12" BEL "u_sru_cmd_par/BusyCnt_11" BEL "u_sru_cmd_par/BusyCnt_10" BEL "u_sru_cmd_par/BusyCnt_9" BEL "u_sru_cmd_par/BusyCnt_8" BEL "u_sru_cmd_par/BusyCnt_7" BEL "u_sru_cmd_par/BusyCnt_6" BEL "u_sru_cmd_par/BusyCnt_5" BEL "u_sru_cmd_par/BusyCnt_4" BEL "u_sru_cmd_par/BusyCnt_3" BEL "u_sru_cmd_par/BusyCnt_2" BEL "u_sru_cmd_par/BusyCnt_1" BEL "u_sru_cmd_par/BusyCnt_0" BEL "u_sru_cmd_par/SRUMonData_15" BEL "u_sru_cmd_par/SRUMonData_14" BEL "u_sru_cmd_par/SRUMonData_13" BEL "u_sru_cmd_par/SRUMonData_12" BEL "u_sru_cmd_par/SRUMonData_11" BEL "u_sru_cmd_par/SRUMonData_10" BEL "u_sru_cmd_par/SRUMonData_9" BEL "u_sru_cmd_par/SRUMonData_8" BEL "u_sru_cmd_par/SRUMonData_7" BEL "u_sru_cmd_par/SRUMonData_6" BEL "u_sru_cmd_par/SRUMonData_5" BEL "u_sru_cmd_par/SRUMonData_4" BEL "u_sru_cmd_par/SRUMonData_3" BEL "u_sru_cmd_par/SRUMonData_2" BEL "u_sru_cmd_par/SRUMonData_1" BEL "u_sru_cmd_par/SRUMonData_0" BEL "u_sru_cmd_par/FastCmdCode_7" BEL "u_sru_cmd_par/FastCmdCode_6" BEL "u_sru_cmd_par/FastCmdCode_5" BEL "u_sru_cmd_par/FastCmdCode_4" BEL "u_sru_cmd_par/FastCmdCode_3" BEL "u_sru_cmd_par/FastCmdCode_2" BEL "u_sru_cmd_par/FastCmdCode_1" BEL "u_sru_cmd_par/FastCmdCode_0" BEL "u_sru_cmd_par/walign_reg_31" BEL "u_sru_cmd_par/walign_reg_30" BEL "u_sru_cmd_par/walign_reg_29" BEL "u_sru_cmd_par/walign_reg_28" BEL "u_sru_cmd_par/walign_reg_27" BEL "u_sru_cmd_par/walign_reg_26" BEL "u_sru_cmd_par/walign_reg_25" BEL "u_sru_cmd_par/walign_reg_24" BEL "u_sru_cmd_par/walign_reg_23" BEL "u_sru_cmd_par/walign_reg_22" BEL "u_sru_cmd_par/walign_reg_21" BEL "u_sru_cmd_par/walign_reg_20" BEL "u_sru_cmd_par/walign_reg_19" BEL "u_sru_cmd_par/walign_reg_18" BEL "u_sru_cmd_par/walign_reg_17" BEL "u_sru_cmd_par/walign_reg_16" BEL "u_sru_cmd_par/walign_reg_15" BEL "u_sru_cmd_par/walign_reg_14" BEL "u_sru_cmd_par/walign_reg_13" BEL "u_sru_cmd_par/walign_reg_12" BEL "u_sru_cmd_par/walign_reg_11" BEL "u_sru_cmd_par/walign_reg_10" BEL "u_sru_cmd_par/walign_reg_9" BEL "u_sru_cmd_par/walign_reg_8" BEL "u_sru_cmd_par/walign_reg_7" BEL "u_sru_cmd_par/walign_reg_6" BEL "u_sru_cmd_par/walign_reg_5" BEL "u_sru_cmd_par/walign_reg_4" BEL "u_sru_cmd_par/walign_reg_3" BEL "u_sru_cmd_par/walign_reg_2" BEL "u_sru_cmd_par/walign_reg_1" BEL "u_sru_cmd_par/walign_reg_0" BEL "u_sru_cmd_par/errtest_reg_31" BEL "u_sru_cmd_par/errtest_reg_30" BEL "u_sru_cmd_par/errtest_reg_29" BEL "u_sru_cmd_par/errtest_reg_28" BEL "u_sru_cmd_par/errtest_reg_27" BEL "u_sru_cmd_par/errtest_reg_26" BEL "u_sru_cmd_par/errtest_reg_25" BEL "u_sru_cmd_par/errtest_reg_24" BEL "u_sru_cmd_par/errtest_reg_23" BEL "u_sru_cmd_par/errtest_reg_22" BEL "u_sru_cmd_par/errtest_reg_21" BEL "u_sru_cmd_par/errtest_reg_20" BEL "u_sru_cmd_par/errtest_reg_19" BEL "u_sru_cmd_par/errtest_reg_18" BEL "u_sru_cmd_par/errtest_reg_17" BEL "u_sru_cmd_par/errtest_reg_16" BEL "u_sru_cmd_par/errtest_reg_15" BEL "u_sru_cmd_par/errtest_reg_14" BEL "u_sru_cmd_par/errtest_reg_13" BEL "u_sru_cmd_par/errtest_reg_12" BEL "u_sru_cmd_par/errtest_reg_11" BEL "u_sru_cmd_par/errtest_reg_10" BEL "u_sru_cmd_par/errtest_reg_9" BEL "u_sru_cmd_par/errtest_reg_8" BEL "u_sru_cmd_par/errtest_reg_7" BEL "u_sru_cmd_par/errtest_reg_6" BEL "u_sru_cmd_par/errtest_reg_5" BEL "u_sru_cmd_par/errtest_reg_4" BEL "u_sru_cmd_par/errtest_reg_3" BEL "u_sru_cmd_par/errtest_reg_2" BEL "u_sru_cmd_par/errtest_reg_1" BEL "u_sru_cmd_par/errtest_reg_0" BEL "u_sru_cmd_par/FastCmd_reg_15" BEL "u_sru_cmd_par/FastCmd_reg_14" BEL "u_sru_cmd_par/FastCmd_reg_13" BEL "u_sru_cmd_par/FastCmd_reg_12" BEL "u_sru_cmd_par/FastCmd_reg_11" BEL "u_sru_cmd_par/FastCmd_reg_10" BEL "u_sru_cmd_par/FastCmd_reg_9" BEL "u_sru_cmd_par/FastCmd_reg_8" BEL "u_sru_cmd_par/FastCmd_reg_7" BEL "u_sru_cmd_par/FastCmd_reg_6" BEL "u_sru_cmd_par/FastCmd_reg_5" BEL "u_sru_cmd_par/FastCmd_reg_4" BEL "u_sru_cmd_par/FastCmd_reg_3" BEL "u_sru_cmd_par/FastCmd_reg_2" BEL "u_sru_cmd_par/FastCmd_reg_1" BEL "u_sru_cmd_par/FastCmd_reg_0" BEL "u_sru_cmd_par/dtc_out_phase_cmd" BEL "u_sru_cmd_par/event_countdown_wr_en" BEL "u_sru_cmd_par/timestamp_clr" BEL "u_sru_cmd_par/busyclr_cmd" BEL "u_sru_cmd_par/trigerr_clr" BEL "u_sru_cmd_par/trigcnt_clr" BEL "u_sru_cmd_par/evnt_clr" BEL "u_sru_cmd_par/pscmd" BEL "u_sru_cmd_par/strig_cmd" BEL "u_sru_cmd_par/FPGAReload_i" BEL "u_sru_cmd_par/errtest_cmd" BEL "u_sru_cmd_par/walign_cmd" BEL "u_sru_cmd_par/test_pulse_width_9" BEL "u_sru_cmd_par/test_pulse_width_8" BEL "u_sru_cmd_par/test_pulse_width_7" BEL "u_sru_cmd_par/test_pulse_width_6" BEL "u_sru_cmd_par/test_pulse_width_5" BEL "u_sru_cmd_par/test_pulse_width_4" BEL "u_sru_cmd_par/test_pulse_width_3" BEL "u_sru_cmd_par/test_pulse_width_2" BEL "u_sru_cmd_par/test_pulse_width_1" BEL "u_sru_cmd_par/test_pulse_width_0" BEL "u_sru_cmd_par/testtrigcfg1_31" BEL "u_sru_cmd_par/testtrigcfg1_30" BEL "u_sru_cmd_par/testtrigcfg1_29" BEL "u_sru_cmd_par/testtrigcfg1_28" BEL "u_sru_cmd_par/testtrigcfg1_27" BEL "u_sru_cmd_par/testtrigcfg1_26" BEL "u_sru_cmd_par/testtrigcfg1_25" BEL "u_sru_cmd_par/testtrigcfg1_24" BEL "u_sru_cmd_par/testtrigcfg1_23" BEL "u_sru_cmd_par/testtrigcfg1_22" BEL "u_sru_cmd_par/testtrigcfg1_21" BEL "u_sru_cmd_par/testtrigcfg1_20" BEL "u_sru_cmd_par/testtrigcfg1_19" BEL "u_sru_cmd_par/testtrigcfg1_18" BEL "u_sru_cmd_par/testtrigcfg1_17" BEL "u_sru_cmd_par/testtrigcfg1_16" BEL "u_sru_cmd_par/testtrigcfg1_15" BEL "u_sru_cmd_par/testtrigcfg1_14" BEL "u_sru_cmd_par/testtrigcfg1_13" BEL "u_sru_cmd_par/testtrigcfg1_12" BEL "u_sru_cmd_par/testtrigcfg1_11" BEL "u_sru_cmd_par/testtrigcfg1_10" BEL "u_sru_cmd_par/testtrigcfg1_9" BEL "u_sru_cmd_par/testtrigcfg1_8" BEL "u_sru_cmd_par/testtrigcfg1_7" BEL "u_sru_cmd_par/testtrigcfg1_6" BEL "u_sru_cmd_par/testtrigcfg1_5" BEL "u_sru_cmd_par/testtrigcfg1_4" BEL "u_sru_cmd_par/testtrigcfg1_3" BEL "u_sru_cmd_par/testtrigcfg1_2" BEL "u_sru_cmd_par/testtrigcfg1_1" BEL "u_sru_cmd_par/testtrigcfg1_0" BEL "u_sru_cmd_par/test_pulse_start_15" BEL "u_sru_cmd_par/test_pulse_start_14" BEL "u_sru_cmd_par/test_pulse_start_13" BEL "u_sru_cmd_par/test_pulse_start_12" BEL "u_sru_cmd_par/test_pulse_start_11" BEL "u_sru_cmd_par/test_pulse_start_10" BEL "u_sru_cmd_par/test_pulse_start_9" BEL "u_sru_cmd_par/test_pulse_start_8" BEL "u_sru_cmd_par/test_pulse_start_7" BEL "u_sru_cmd_par/test_pulse_start_6" BEL "u_sru_cmd_par/test_pulse_start_5" BEL "u_sru_cmd_par/test_pulse_start_4" BEL "u_sru_cmd_par/test_pulse_start_3" BEL "u_sru_cmd_par/test_pulse_start_2" BEL "u_sru_cmd_par/test_pulse_start_1" BEL "u_sru_cmd_par/test_pulse_start_0" BEL "u_sru_cmd_par/ptrigcfg_16" BEL "u_sru_cmd_par/ptrigcfg_15" BEL "u_sru_cmd_par/ptrigcfg_14" BEL "u_sru_cmd_par/ptrigcfg_13" BEL "u_sru_cmd_par/ptrigcfg_12" BEL "u_sru_cmd_par/ptrigcfg_11" BEL "u_sru_cmd_par/ptrigcfg_10" BEL "u_sru_cmd_par/ptrigcfg_9" BEL "u_sru_cmd_par/ptrigcfg_8" BEL "u_sru_cmd_par/ptrigcfg_7" BEL "u_sru_cmd_par/ptrigcfg_6" BEL "u_sru_cmd_par/ptrigcfg_5" BEL "u_sru_cmd_par/ptrigcfg_4" BEL "u_sru_cmd_par/ptrigcfg_3" BEL "u_sru_cmd_par/ptrigcfg_2" BEL "u_sru_cmd_par/ptrigcfg_1" BEL "u_sru_cmd_par/ptrigcfg_0" BEL "u_sru_cmd_par/trigl2tw_31" BEL "u_sru_cmd_par/trigl2tw_30" BEL "u_sru_cmd_par/trigl2tw_29" BEL "u_sru_cmd_par/trigl2tw_28" BEL "u_sru_cmd_par/trigl2tw_27" BEL "u_sru_cmd_par/trigl2tw_26" BEL "u_sru_cmd_par/trigl2tw_25" BEL "u_sru_cmd_par/trigl2tw_24" BEL "u_sru_cmd_par/trigl2tw_23" BEL "u_sru_cmd_par/trigl2tw_22" BEL "u_sru_cmd_par/trigl2tw_21" BEL "u_sru_cmd_par/trigl2tw_20" BEL "u_sru_cmd_par/trigl2tw_19" BEL "u_sru_cmd_par/trigl2tw_18" BEL "u_sru_cmd_par/trigl2tw_17" BEL "u_sru_cmd_par/trigl2tw_16" BEL "u_sru_cmd_par/trigl2tw_15" BEL "u_sru_cmd_par/trigl2tw_14" BEL "u_sru_cmd_par/trigl2tw_13" BEL "u_sru_cmd_par/trigl2tw_12" BEL "u_sru_cmd_par/trigl2tw_11" BEL "u_sru_cmd_par/trigl2tw_10" BEL "u_sru_cmd_par/trigl2tw_9" BEL "u_sru_cmd_par/trigl2tw_8" BEL "u_sru_cmd_par/trigl2tw_7" BEL "u_sru_cmd_par/trigl2tw_6" BEL "u_sru_cmd_par/trigl2tw_5" BEL "u_sru_cmd_par/trigl2tw_4" BEL "u_sru_cmd_par/trigl2tw_3" BEL "u_sru_cmd_par/trigl2tw_2" BEL "u_sru_cmd_par/trigl2tw_1" BEL "u_sru_cmd_par/trigl2tw_0" BEL "u_sru_cmd_par/testtrigcfg0_31" BEL "u_sru_cmd_par/testtrigcfg0_30" BEL "u_sru_cmd_par/testtrigcfg0_29" BEL "u_sru_cmd_par/testtrigcfg0_28" BEL "u_sru_cmd_par/testtrigcfg0_27" BEL "u_sru_cmd_par/testtrigcfg0_26" BEL "u_sru_cmd_par/testtrigcfg0_25" BEL "u_sru_cmd_par/testtrigcfg0_24" BEL "u_sru_cmd_par/testtrigcfg0_23" BEL "u_sru_cmd_par/testtrigcfg0_22" BEL "u_sru_cmd_par/testtrigcfg0_21" BEL "u_sru_cmd_par/testtrigcfg0_20" BEL "u_sru_cmd_par/testtrigcfg0_19" BEL "u_sru_cmd_par/testtrigcfg0_18" BEL "u_sru_cmd_par/testtrigcfg0_17" BEL "u_sru_cmd_par/testtrigcfg0_16" BEL "u_sru_cmd_par/testtrigcfg0_15" BEL "u_sru_cmd_par/testtrigcfg0_14" BEL "u_sru_cmd_par/testtrigcfg0_13" BEL "u_sru_cmd_par/testtrigcfg0_12" BEL "u_sru_cmd_par/testtrigcfg0_11" BEL "u_sru_cmd_par/testtrigcfg0_10" BEL "u_sru_cmd_par/testtrigcfg0_9" BEL "u_sru_cmd_par/testtrigcfg0_8" BEL "u_sru_cmd_par/testtrigcfg0_7" BEL "u_sru_cmd_par/testtrigcfg0_6" BEL "u_sru_cmd_par/testtrigcfg0_5" BEL "u_sru_cmd_par/testtrigcfg0_4" BEL "u_sru_cmd_par/testtrigcfg0_3" BEL "u_sru_cmd_par/testtrigcfg0_2" BEL "u_sru_cmd_par/testtrigcfg0_1" BEL "u_sru_cmd_par/testtrigcfg0_0" BEL "u_sru_cmd_par/trigl1tw_31" BEL "u_sru_cmd_par/trigl1tw_30" BEL "u_sru_cmd_par/trigl1tw_29" BEL "u_sru_cmd_par/trigl1tw_28" BEL "u_sru_cmd_par/trigl1tw_27" BEL "u_sru_cmd_par/trigl1tw_26" BEL "u_sru_cmd_par/trigl1tw_25" BEL "u_sru_cmd_par/trigl1tw_24" BEL "u_sru_cmd_par/trigl1tw_23" BEL "u_sru_cmd_par/trigl1tw_22" BEL "u_sru_cmd_par/trigl1tw_21" BEL "u_sru_cmd_par/trigl1tw_20" BEL "u_sru_cmd_par/trigl1tw_19" BEL "u_sru_cmd_par/trigl1tw_18" BEL "u_sru_cmd_par/trigl1tw_17" BEL "u_sru_cmd_par/trigl1tw_16" BEL "u_sru_cmd_par/trigl1tw_15" BEL "u_sru_cmd_par/trigl1tw_14" BEL "u_sru_cmd_par/trigl1tw_13" BEL "u_sru_cmd_par/trigl1tw_12" BEL "u_sru_cmd_par/trigl1tw_11" BEL "u_sru_cmd_par/trigl1tw_10" BEL "u_sru_cmd_par/trigl1tw_9" BEL "u_sru_cmd_par/trigl1tw_8" BEL "u_sru_cmd_par/trigl1tw_7" BEL "u_sru_cmd_par/trigl1tw_6" BEL "u_sru_cmd_par/trigl1tw_5" BEL "u_sru_cmd_par/trigl1tw_4" BEL "u_sru_cmd_par/trigl1tw_3" BEL "u_sru_cmd_par/trigl1tw_2" BEL "u_sru_cmd_par/trigl1tw_1" BEL "u_sru_cmd_par/trigl1tw_0" BEL "u_sru_cmd_par/psscancfg_16" BEL "u_sru_cmd_par/psscancfg_15" BEL "u_sru_cmd_par/psscancfg_14" BEL "u_sru_cmd_par/psscancfg_13" BEL "u_sru_cmd_par/psscancfg_12" BEL "u_sru_cmd_par/psscancfg_11" BEL "u_sru_cmd_par/psscancfg_10" BEL "u_sru_cmd_par/psscancfg_9" BEL "u_sru_cmd_par/psscancfg_8" BEL "u_sru_cmd_par/psscancfg_7" BEL "u_sru_cmd_par/psscancfg_6" BEL "u_sru_cmd_par/psscancfg_5" BEL "u_sru_cmd_par/psscancfg_4" BEL "u_sru_cmd_par/psscancfg_3" BEL "u_sru_cmd_par/psscancfg_2" BEL "u_sru_cmd_par/psscancfg_1" BEL "u_sru_cmd_par/psscancfg_0" BEL "u_sru_cmd_par/dtc_power_en_39" BEL "u_sru_cmd_par/dtc_power_en_38" BEL "u_sru_cmd_par/dtc_power_en_37" BEL "u_sru_cmd_par/dtc_power_en_36" BEL "u_sru_cmd_par/dtc_power_en_35" BEL "u_sru_cmd_par/dtc_power_en_34" BEL "u_sru_cmd_par/dtc_power_en_33" BEL "u_sru_cmd_par/dtc_power_en_32" BEL "u_sru_cmd_par/dtc_power_en_31" BEL "u_sru_cmd_par/dtc_power_en_30" BEL "u_sru_cmd_par/dtc_power_en_29" BEL "u_sru_cmd_par/dtc_power_en_28" BEL "u_sru_cmd_par/dtc_power_en_27" BEL "u_sru_cmd_par/dtc_power_en_26" BEL "u_sru_cmd_par/dtc_power_en_25" BEL "u_sru_cmd_par/dtc_power_en_24" BEL "u_sru_cmd_par/dtc_power_en_23" BEL "u_sru_cmd_par/dtc_power_en_22" BEL "u_sru_cmd_par/dtc_power_en_21" BEL "u_sru_cmd_par/dtc_power_en_20" BEL "u_sru_cmd_par/dtc_power_en_19" BEL "u_sru_cmd_par/dtc_power_en_18" BEL "u_sru_cmd_par/dtc_power_en_17" BEL "u_sru_cmd_par/dtc_power_en_16" BEL "u_sru_cmd_par/dtc_power_en_15" BEL "u_sru_cmd_par/dtc_power_en_14" BEL "u_sru_cmd_par/dtc_power_en_13" BEL "u_sru_cmd_par/dtc_power_en_12" BEL "u_sru_cmd_par/dtc_power_en_11" BEL "u_sru_cmd_par/dtc_power_en_10" BEL "u_sru_cmd_par/dtc_power_en_9" BEL "u_sru_cmd_par/dtc_power_en_8" BEL "u_sru_cmd_par/dtc_power_en_7" BEL "u_sru_cmd_par/dtc_power_en_6" BEL "u_sru_cmd_par/dtc_power_en_5" BEL "u_sru_cmd_par/dtc_power_en_4" BEL "u_sru_cmd_par/dtc_power_en_3" BEL "u_sru_cmd_par/dtc_power_en_2" BEL "u_sru_cmd_par/dtc_power_en_1" BEL "u_sru_cmd_par/dtc_power_en_0" BEL "u_sru_cmd_par/dtc_out_phase_delay_4" BEL "u_sru_cmd_par/dtc_out_phase_delay_3" BEL "u_sru_cmd_par/dtc_out_phase_delay_2" BEL "u_sru_cmd_par/dtc_out_phase_delay_1" BEL "u_sru_cmd_par/dtc_out_phase_delay_0" BEL "u_sru_cmd_par/dtc_out_phase_channel_5" BEL "u_sru_cmd_par/dtc_out_phase_channel_4" BEL "u_sru_cmd_par/dtc_out_phase_channel_3" BEL "u_sru_cmd_par/dtc_out_phase_channel_2" BEL "u_sru_cmd_par/dtc_out_phase_channel_1" BEL "u_sru_cmd_par/dtc_out_phase_channel_0" BEL "u_sru_cmd_par/event_countdown_input_31" BEL "u_sru_cmd_par/event_countdown_input_30" BEL "u_sru_cmd_par/event_countdown_input_29" BEL "u_sru_cmd_par/event_countdown_input_28" BEL "u_sru_cmd_par/event_countdown_input_27" BEL "u_sru_cmd_par/event_countdown_input_26" BEL "u_sru_cmd_par/event_countdown_input_25" BEL "u_sru_cmd_par/event_countdown_input_24" BEL "u_sru_cmd_par/event_countdown_input_23" BEL "u_sru_cmd_par/event_countdown_input_22" BEL "u_sru_cmd_par/event_countdown_input_21" BEL "u_sru_cmd_par/event_countdown_input_20" BEL "u_sru_cmd_par/event_countdown_input_19" BEL "u_sru_cmd_par/event_countdown_input_18" BEL "u_sru_cmd_par/event_countdown_input_17" BEL "u_sru_cmd_par/event_countdown_input_16" BEL "u_sru_cmd_par/event_countdown_input_15" BEL "u_sru_cmd_par/event_countdown_input_14" BEL "u_sru_cmd_par/event_countdown_input_13" BEL "u_sru_cmd_par/event_countdown_input_12" BEL "u_sru_cmd_par/event_countdown_input_11" BEL "u_sru_cmd_par/event_countdown_input_10" BEL "u_sru_cmd_par/event_countdown_input_9" BEL "u_sru_cmd_par/event_countdown_input_8" BEL "u_sru_cmd_par/event_countdown_input_7" BEL "u_sru_cmd_par/event_countdown_input_6" BEL "u_sru_cmd_par/event_countdown_input_5" BEL "u_sru_cmd_par/event_countdown_input_4" BEL "u_sru_cmd_par/event_countdown_input_3" BEL "u_sru_cmd_par/event_countdown_input_2" BEL "u_sru_cmd_par/event_countdown_input_1" BEL "u_sru_cmd_par/event_countdown_input_0" BEL "u_sru_cmd_par/dtc_mon_sel_5" BEL "u_sru_cmd_par/dtc_mon_sel_4" BEL "u_sru_cmd_par/dtc_mon_sel_3" BEL "u_sru_cmd_par/dtc_mon_sel_2" BEL "u_sru_cmd_par/dtc_mon_sel_1" BEL "u_sru_cmd_par/dtc_mon_sel_0" BEL "u_sru_cmd_par/readout_ip_31" BEL "u_sru_cmd_par/readout_ip_30" BEL "u_sru_cmd_par/readout_ip_29" BEL "u_sru_cmd_par/readout_ip_28" BEL "u_sru_cmd_par/readout_ip_27" BEL "u_sru_cmd_par/readout_ip_26" BEL "u_sru_cmd_par/readout_ip_25" BEL "u_sru_cmd_par/readout_ip_24" BEL "u_sru_cmd_par/readout_ip_23" BEL "u_sru_cmd_par/readout_ip_22" BEL "u_sru_cmd_par/readout_ip_21" BEL "u_sru_cmd_par/readout_ip_20" BEL "u_sru_cmd_par/readout_ip_19" BEL "u_sru_cmd_par/readout_ip_18" BEL "u_sru_cmd_par/readout_ip_17" BEL "u_sru_cmd_par/readout_ip_16" BEL "u_sru_cmd_par/readout_ip_15" BEL "u_sru_cmd_par/readout_ip_14" BEL "u_sru_cmd_par/readout_ip_13" BEL "u_sru_cmd_par/readout_ip_12" BEL "u_sru_cmd_par/readout_ip_11" BEL "u_sru_cmd_par/readout_ip_10" BEL "u_sru_cmd_par/readout_ip_9" BEL "u_sru_cmd_par/readout_ip_8" BEL "u_sru_cmd_par/readout_ip_7" BEL "u_sru_cmd_par/readout_ip_6" BEL "u_sru_cmd_par/readout_ip_5" BEL "u_sru_cmd_par/readout_ip_4" BEL "u_sru_cmd_par/readout_ip_3" BEL "u_sru_cmd_par/readout_ip_2" BEL "u_sru_cmd_par/readout_ip_1" BEL "u_sru_cmd_par/readout_ip_0" BEL "u_sru_cmd_par/SruMonAddr_6" BEL "u_sru_cmd_par/SruMonAddr_5" BEL "u_sru_cmd_par/SruMonAddr_4" BEL "u_sru_cmd_par/SruMonAddr_3" BEL "u_sru_cmd_par/SruMonAddr_2" BEL "u_sru_cmd_par/SruMonAddr_1" BEL "u_sru_cmd_par/SruMonAddr_0" BEL "u_sru_cmd_par/srucfg_31" BEL "u_sru_cmd_par/srucfg_30" BEL "u_sru_cmd_par/srucfg_29" BEL "u_sru_cmd_par/srucfg_28" BEL "u_sru_cmd_par/srucfg_27" BEL "u_sru_cmd_par/srucfg_26" BEL "u_sru_cmd_par/srucfg_25" BEL "u_sru_cmd_par/srucfg_24" BEL "u_sru_cmd_par/srucfg_23" BEL "u_sru_cmd_par/srucfg_22" BEL "u_sru_cmd_par/srucfg_21" BEL "u_sru_cmd_par/srucfg_20" BEL "u_sru_cmd_par/srucfg_19" BEL "u_sru_cmd_par/srucfg_18" BEL "u_sru_cmd_par/srucfg_17" BEL "u_sru_cmd_par/srucfg_16" BEL "u_sru_cmd_par/srucfg_15" BEL "u_sru_cmd_par/srucfg_14" BEL "u_sru_cmd_par/srucfg_13" BEL "u_sru_cmd_par/srucfg_12" BEL "u_sru_cmd_par/srucfg_11" BEL "u_sru_cmd_par/srucfg_10" BEL "u_sru_cmd_par/srucfg_9" BEL "u_sru_cmd_par/srucfg_8" BEL "u_sru_cmd_par/srucfg_7" BEL "u_sru_cmd_par/srucfg_6" BEL "u_sru_cmd_par/srucfg_5" BEL "u_sru_cmd_par/srucfg_4" BEL "u_sru_cmd_par/srucfg_3" BEL "u_sru_cmd_par/srucfg_2" BEL "u_sru_cmd_par/srucfg_1" BEL "u_sru_cmd_par/srucfg_0" BEL "u_sru_cmd_par/altrocfg_39" BEL "u_sru_cmd_par/altrocfg_38" BEL "u_sru_cmd_par/altrocfg_37" BEL "u_sru_cmd_par/altrocfg_36" BEL "u_sru_cmd_par/altrocfg_35" BEL "u_sru_cmd_par/altrocfg_34" BEL "u_sru_cmd_par/altrocfg_33" BEL "u_sru_cmd_par/altrocfg_32" BEL "u_sru_cmd_par/altrocfg_31" BEL "u_sru_cmd_par/altrocfg_30" BEL "u_sru_cmd_par/altrocfg_29" BEL "u_sru_cmd_par/altrocfg_28" BEL "u_sru_cmd_par/altrocfg_27" BEL "u_sru_cmd_par/altrocfg_26" BEL "u_sru_cmd_par/altrocfg_25" BEL "u_sru_cmd_par/altrocfg_24" BEL "u_sru_cmd_par/altrocfg_23" BEL "u_sru_cmd_par/altrocfg_22" BEL "u_sru_cmd_par/altrocfg_21" BEL "u_sru_cmd_par/altrocfg_20" BEL "u_sru_cmd_par/altrocfg_19" BEL "u_sru_cmd_par/altrocfg_18" BEL "u_sru_cmd_par/altrocfg_17" BEL "u_sru_cmd_par/altrocfg_16" BEL "u_sru_cmd_par/altrocfg_15" BEL "u_sru_cmd_par/altrocfg_14" BEL "u_sru_cmd_par/altrocfg_13" BEL "u_sru_cmd_par/altrocfg_12" BEL "u_sru_cmd_par/altrocfg_11" BEL "u_sru_cmd_par/altrocfg_10" BEL "u_sru_cmd_par/altrocfg_9" BEL "u_sru_cmd_par/altrocfg_8" BEL "u_sru_cmd_par/altrocfg_7" BEL "u_sru_cmd_par/altrocfg_6" BEL "u_sru_cmd_par/altrocfg_5" BEL "u_sru_cmd_par/altrocfg_4" BEL "u_sru_cmd_par/altrocfg_3" BEL "u_sru_cmd_par/altrocfg_2" BEL "u_sru_cmd_par/altrocfg_1" BEL "u_sru_cmd_par/altrocfg_0" BEL "u_sru_cmd_par/dtc_rdo_mask_i_39" BEL "u_sru_cmd_par/dtc_rdo_mask_i_38" BEL "u_sru_cmd_par/dtc_rdo_mask_i_37" BEL "u_sru_cmd_par/dtc_rdo_mask_i_36" BEL "u_sru_cmd_par/dtc_rdo_mask_i_35" BEL "u_sru_cmd_par/dtc_rdo_mask_i_34" BEL "u_sru_cmd_par/dtc_rdo_mask_i_33" BEL "u_sru_cmd_par/dtc_rdo_mask_i_32" BEL "u_sru_cmd_par/dtc_rdo_mask_i_31" BEL "u_sru_cmd_par/dtc_rdo_mask_i_30" BEL "u_sru_cmd_par/dtc_rdo_mask_i_29" BEL "u_sru_cmd_par/dtc_rdo_mask_i_28" BEL "u_sru_cmd_par/dtc_rdo_mask_i_27" BEL "u_sru_cmd_par/dtc_rdo_mask_i_26" BEL "u_sru_cmd_par/dtc_rdo_mask_i_25" BEL "u_sru_cmd_par/dtc_rdo_mask_i_24" BEL "u_sru_cmd_par/dtc_rdo_mask_i_23" BEL "u_sru_cmd_par/dtc_rdo_mask_i_22" BEL "u_sru_cmd_par/dtc_rdo_mask_i_21" BEL "u_sru_cmd_par/dtc_rdo_mask_i_20" BEL "u_sru_cmd_par/dtc_rdo_mask_i_19" BEL "u_sru_cmd_par/dtc_rdo_mask_i_18" BEL "u_sru_cmd_par/dtc_rdo_mask_i_17" BEL "u_sru_cmd_par/dtc_rdo_mask_i_16" BEL "u_sru_cmd_par/dtc_rdo_mask_i_15" BEL "u_sru_cmd_par/dtc_rdo_mask_i_14" BEL "u_sru_cmd_par/dtc_rdo_mask_i_13" BEL "u_sru_cmd_par/dtc_rdo_mask_i_12" BEL "u_sru_cmd_par/dtc_rdo_mask_i_11" BEL "u_sru_cmd_par/dtc_rdo_mask_i_10" BEL "u_sru_cmd_par/dtc_rdo_mask_i_9" BEL "u_sru_cmd_par/dtc_rdo_mask_i_8" BEL "u_sru_cmd_par/dtc_rdo_mask_i_7" BEL "u_sru_cmd_par/dtc_rdo_mask_i_6" BEL "u_sru_cmd_par/dtc_rdo_mask_i_5" BEL "u_sru_cmd_par/dtc_rdo_mask_i_4" BEL "u_sru_cmd_par/dtc_rdo_mask_i_3" BEL "u_sru_cmd_par/dtc_rdo_mask_i_2" BEL "u_sru_cmd_par/dtc_rdo_mask_i_1" BEL "u_sru_cmd_par/dtc_rdo_mask_i_0" BEL "u_sru_cmd_par/rcmd_reply_dv" BEL "u_sru_cmd_par/rcmd_reply_data_31" BEL "u_sru_cmd_par/rcmd_reply_data_30" BEL "u_sru_cmd_par/rcmd_reply_data_29" BEL "u_sru_cmd_par/rcmd_reply_data_28" BEL "u_sru_cmd_par/rcmd_reply_data_27" BEL "u_sru_cmd_par/rcmd_reply_data_26" BEL "u_sru_cmd_par/rcmd_reply_data_25" BEL "u_sru_cmd_par/rcmd_reply_data_24" BEL "u_sru_cmd_par/rcmd_reply_data_23" BEL "u_sru_cmd_par/rcmd_reply_data_22" BEL "u_sru_cmd_par/rcmd_reply_data_21" BEL "u_sru_cmd_par/rcmd_reply_data_20" BEL "u_sru_cmd_par/rcmd_reply_data_19" BEL "u_sru_cmd_par/rcmd_reply_data_18" BEL "u_sru_cmd_par/rcmd_reply_data_17" BEL "u_sru_cmd_par/rcmd_reply_data_16" BEL "u_sru_cmd_par/rcmd_reply_data_15" BEL "u_sru_cmd_par/rcmd_reply_data_14" BEL "u_sru_cmd_par/rcmd_reply_data_13" BEL "u_sru_cmd_par/rcmd_reply_data_12" BEL "u_sru_cmd_par/rcmd_reply_data_11" BEL "u_sru_cmd_par/rcmd_reply_data_10" BEL "u_sru_cmd_par/rcmd_reply_data_9" BEL "u_sru_cmd_par/rcmd_reply_data_8" BEL "u_sru_cmd_par/rcmd_reply_data_7" BEL "u_sru_cmd_par/rcmd_reply_data_6" BEL "u_sru_cmd_par/rcmd_reply_data_5" BEL "u_sru_cmd_par/rcmd_reply_data_4" BEL "u_sru_cmd_par/rcmd_reply_data_3" BEL "u_sru_cmd_par/rcmd_reply_data_2" BEL "u_sru_cmd_par/rcmd_reply_data_1" BEL "u_sru_cmd_par/rcmd_reply_data_0" BEL "u_sru_cmd_par/spill_d" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL 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"u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_cmd_par/FastCmd_i" BEL "u_sru_cmd_par/test_pulse_en" BEL "htrig_d" BEL "spill_sync_d" BEL "sru_trig_synced_out_nim" BEL "u_sru_40dtc_top/DTCRamAllFlag_i" BEL "u_sru_cmd_par/reset_cmd" BEL "u_sru_trigger/tlu_event_number_15" BEL "u_sru_trigger/tlu_event_number_14" BEL "u_sru_trigger/tlu_event_number_13" BEL "u_sru_trigger/tlu_event_number_12" BEL "u_sru_trigger/tlu_event_number_11" BEL "u_sru_trigger/tlu_event_number_10" BEL "u_sru_trigger/tlu_event_number_9" BEL "u_sru_trigger/tlu_event_number_8" BEL "u_sru_trigger/tlu_event_number_7" BEL "u_sru_trigger/tlu_event_number_6" BEL "u_sru_trigger/tlu_event_number_5" BEL "u_sru_trigger/tlu_event_number_4" BEL "u_sru_trigger/tlu_event_number_3" BEL "u_sru_trigger/tlu_event_number_2" BEL "u_sru_trigger/tlu_event_number_1" BEL "u_sru_trigger/tlu_event_number_0" BEL "u_sru_trigger/tlu_event_number_shift_16" BEL "u_sru_trigger/tlu_event_number_shift_15" BEL "u_sru_trigger/tlu_event_number_shift_14" BEL "u_sru_trigger/tlu_event_number_shift_13" BEL "u_sru_trigger/tlu_event_number_shift_12" BEL "u_sru_trigger/tlu_event_number_shift_11" BEL "u_sru_trigger/tlu_event_number_shift_10" BEL "u_sru_trigger/tlu_event_number_shift_9" BEL "u_sru_trigger/tlu_event_number_shift_8" BEL "u_sru_trigger/tlu_event_number_shift_7" BEL "u_sru_trigger/tlu_event_number_shift_6" BEL "u_sru_trigger/tlu_event_number_shift_5" BEL "u_sru_trigger/tlu_event_number_shift_4" BEL "u_sru_trigger/tlu_event_number_shift_3" BEL "u_sru_trigger/tlu_event_number_shift_2" BEL "u_sru_trigger/tlu_event_number_shift_1" BEL "u_sru_trigger/tlu_event_number_shift_0" BEL "u_sru_trigger/u_ttc_decoder/st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/ttc_l1" BEL "u_sru_trigger/u_ttc_decoder/ttc_l0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_31" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_30" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_29" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_28" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_27" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_26" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_25" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_24" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_23" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_22" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_21" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_20" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_19" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_18" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_17" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_16" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_15" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_14" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_13" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_23" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_22" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_21" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_20" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_19" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_18" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_17" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_16" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_15" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_14" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_13" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/ttc_l2r" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/ttc_l2aMesRdy" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_59" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_58" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_57" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_56" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_55" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_54" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_53" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_52" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_51" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_50" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_49" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_48" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_47" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_46" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_45" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_44" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_43" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_42" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_41" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_40" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_39" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_38" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_37" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_36" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_35" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_34" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_33" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_32" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_31" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_30" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_29" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_28" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_27" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_26" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_25" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_24" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_23" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_22" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_21" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_20" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_19" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_18" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_17" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_16" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_15" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_14" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_13" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_12" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_11" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_10" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_9" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_8" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_7" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_6" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_5" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_4" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_3" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_2" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_1" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_0" BEL "u_sru_trigger/u_trig_cnt/event_cnt_29" BEL "u_sru_trigger/u_trig_cnt/event_cnt_28" BEL "u_sru_trigger/u_trig_cnt/event_cnt_27" BEL "u_sru_trigger/u_trig_cnt/event_cnt_26" BEL "u_sru_trigger/u_trig_cnt/event_cnt_25" BEL "u_sru_trigger/u_trig_cnt/event_cnt_24" BEL "u_sru_trigger/u_trig_cnt/event_cnt_23" BEL "u_sru_trigger/u_trig_cnt/event_cnt_22" BEL "u_sru_trigger/u_trig_cnt/event_cnt_21" BEL "u_sru_trigger/u_trig_cnt/event_cnt_20" BEL "u_sru_trigger/u_trig_cnt/event_cnt_19" BEL "u_sru_trigger/u_trig_cnt/event_cnt_18" BEL "u_sru_trigger/u_trig_cnt/event_cnt_17" BEL "u_sru_trigger/u_trig_cnt/event_cnt_16" BEL "u_sru_trigger/u_trig_cnt/event_cnt_15" BEL "u_sru_trigger/u_trig_cnt/event_cnt_14" BEL "u_sru_trigger/u_trig_cnt/event_cnt_13" BEL "u_sru_trigger/u_trig_cnt/event_cnt_12" BEL "u_sru_trigger/u_trig_cnt/event_cnt_11" BEL "u_sru_trigger/u_trig_cnt/event_cnt_10" BEL "u_sru_trigger/u_trig_cnt/event_cnt_9" BEL "u_sru_trigger/u_trig_cnt/event_cnt_8" BEL "u_sru_trigger/u_trig_cnt/event_cnt_7" BEL "u_sru_trigger/u_trig_cnt/event_cnt_6" BEL "u_sru_trigger/u_trig_cnt/event_cnt_5" BEL "u_sru_trigger/u_trig_cnt/event_cnt_4" BEL "u_sru_trigger/u_trig_cnt/event_cnt_3" BEL "u_sru_trigger/u_trig_cnt/event_cnt_2" BEL "u_sru_trigger/u_trig_cnt/event_cnt_1" BEL "u_sru_trigger/u_trig_cnt/event_cnt_0" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_31" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_30" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_29" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_28" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_27" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_26" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_25" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_24" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_23" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_22" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_21" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_20" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_19" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_18" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_17" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_16" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_15" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_14" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_13" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_12" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_11" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_10" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_9" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_8" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_7" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_6" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_5" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_4" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_3" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_2" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_1" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_0" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_31" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_30" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_29" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_28" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_27" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_26" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_25" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_24" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_23" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_22" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_21" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_20" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_19" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_18" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_17" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_16" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_15" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_14" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_13" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_12" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_11" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_10" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_9" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_8" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_7" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_6" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_5" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_4" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_3" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_2" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_1" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_0" BEL "u_sru_trigger/u_trig_cnt/event_countdown_31" BEL "u_sru_trigger/u_trig_cnt/event_countdown_30" BEL "u_sru_trigger/u_trig_cnt/event_countdown_29" BEL "u_sru_trigger/u_trig_cnt/event_countdown_28" BEL "u_sru_trigger/u_trig_cnt/event_countdown_27" BEL "u_sru_trigger/u_trig_cnt/event_countdown_26" BEL "u_sru_trigger/u_trig_cnt/event_countdown_25" BEL "u_sru_trigger/u_trig_cnt/event_countdown_24" BEL "u_sru_trigger/u_trig_cnt/event_countdown_23" BEL "u_sru_trigger/u_trig_cnt/event_countdown_22" BEL "u_sru_trigger/u_trig_cnt/event_countdown_21" BEL "u_sru_trigger/u_trig_cnt/event_countdown_20" BEL "u_sru_trigger/u_trig_cnt/event_countdown_19" BEL "u_sru_trigger/u_trig_cnt/event_countdown_18" BEL "u_sru_trigger/u_trig_cnt/event_countdown_17" BEL "u_sru_trigger/u_trig_cnt/event_countdown_16" BEL "u_sru_trigger/u_trig_cnt/event_countdown_15" BEL "u_sru_trigger/u_trig_cnt/event_countdown_14" BEL "u_sru_trigger/u_trig_cnt/event_countdown_13" BEL "u_sru_trigger/u_trig_cnt/event_countdown_12" BEL "u_sru_trigger/u_trig_cnt/event_countdown_11" BEL "u_sru_trigger/u_trig_cnt/event_countdown_10" BEL "u_sru_trigger/u_trig_cnt/event_countdown_9" BEL "u_sru_trigger/u_trig_cnt/event_countdown_8" BEL "u_sru_trigger/u_trig_cnt/event_countdown_7" BEL "u_sru_trigger/u_trig_cnt/event_countdown_6" BEL "u_sru_trigger/u_trig_cnt/event_countdown_5" BEL "u_sru_trigger/u_trig_cnt/event_countdown_4" BEL "u_sru_trigger/u_trig_cnt/event_countdown_3" BEL "u_sru_trigger/u_trig_cnt/event_countdown_2" BEL "u_sru_trigger/u_trig_cnt/event_countdown_1" BEL "u_sru_trigger/u_trig_cnt/event_countdown_0" BEL "u_sru_trigger/u_trig_cnt/clkcntb_3" BEL "u_sru_trigger/u_trig_cnt/clkcntb_2" BEL "u_sru_trigger/u_trig_cnt/clkcntb_1" BEL "u_sru_trigger/u_trig_cnt/clkcntb_0" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/timestamp_59" BEL "u_sru_trigger/u_trig_cnt/timestamp_58" BEL "u_sru_trigger/u_trig_cnt/timestamp_57" BEL "u_sru_trigger/u_trig_cnt/timestamp_56" BEL "u_sru_trigger/u_trig_cnt/timestamp_55" BEL "u_sru_trigger/u_trig_cnt/timestamp_54" BEL "u_sru_trigger/u_trig_cnt/timestamp_53" BEL "u_sru_trigger/u_trig_cnt/timestamp_52" BEL "u_sru_trigger/u_trig_cnt/timestamp_51" BEL "u_sru_trigger/u_trig_cnt/timestamp_50" BEL "u_sru_trigger/u_trig_cnt/timestamp_49" BEL "u_sru_trigger/u_trig_cnt/timestamp_48" BEL "u_sru_trigger/u_trig_cnt/timestamp_47" BEL "u_sru_trigger/u_trig_cnt/timestamp_46" BEL "u_sru_trigger/u_trig_cnt/timestamp_45" BEL "u_sru_trigger/u_trig_cnt/timestamp_44" BEL "u_sru_trigger/u_trig_cnt/timestamp_43" BEL "u_sru_trigger/u_trig_cnt/timestamp_42" BEL "u_sru_trigger/u_trig_cnt/timestamp_41" BEL "u_sru_trigger/u_trig_cnt/timestamp_40" BEL "u_sru_trigger/u_trig_cnt/timestamp_39" BEL "u_sru_trigger/u_trig_cnt/timestamp_38" BEL "u_sru_trigger/u_trig_cnt/timestamp_37" BEL "u_sru_trigger/u_trig_cnt/timestamp_36" BEL "u_sru_trigger/u_trig_cnt/timestamp_35" BEL "u_sru_trigger/u_trig_cnt/timestamp_34" BEL "u_sru_trigger/u_trig_cnt/timestamp_33" BEL "u_sru_trigger/u_trig_cnt/timestamp_32" BEL "u_sru_trigger/u_trig_cnt/timestamp_31" BEL "u_sru_trigger/u_trig_cnt/timestamp_30" BEL "u_sru_trigger/u_trig_cnt/timestamp_29" BEL "u_sru_trigger/u_trig_cnt/timestamp_28" BEL "u_sru_trigger/u_trig_cnt/timestamp_27" BEL "u_sru_trigger/u_trig_cnt/timestamp_26" BEL "u_sru_trigger/u_trig_cnt/timestamp_25" BEL "u_sru_trigger/u_trig_cnt/timestamp_24" BEL "u_sru_trigger/u_trig_cnt/timestamp_23" BEL "u_sru_trigger/u_trig_cnt/timestamp_22" BEL "u_sru_trigger/u_trig_cnt/timestamp_21" BEL "u_sru_trigger/u_trig_cnt/timestamp_20" BEL "u_sru_trigger/u_trig_cnt/timestamp_19" BEL "u_sru_trigger/u_trig_cnt/timestamp_18" BEL "u_sru_trigger/u_trig_cnt/timestamp_17" BEL "u_sru_trigger/u_trig_cnt/timestamp_16" BEL "u_sru_trigger/u_trig_cnt/timestamp_15" BEL "u_sru_trigger/u_trig_cnt/timestamp_14" BEL "u_sru_trigger/u_trig_cnt/timestamp_13" BEL "u_sru_trigger/u_trig_cnt/timestamp_12" BEL "u_sru_trigger/u_trig_cnt/timestamp_11" BEL "u_sru_trigger/u_trig_cnt/timestamp_10" BEL "u_sru_trigger/u_trig_cnt/timestamp_9" BEL "u_sru_trigger/u_trig_cnt/timestamp_8" BEL "u_sru_trigger/u_trig_cnt/timestamp_7" BEL "u_sru_trigger/u_trig_cnt/timestamp_6" BEL "u_sru_trigger/u_trig_cnt/timestamp_5" BEL "u_sru_trigger/u_trig_cnt/timestamp_4" BEL "u_sru_trigger/u_trig_cnt/timestamp_3" BEL "u_sru_trigger/u_trig_cnt/timestamp_2" BEL "u_sru_trigger/u_trig_cnt/timestamp_1" BEL "u_sru_trigger/u_trig_cnt/timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/abortcmd" BEL "u_sru_trigger/u_trig_cnt/rdocmd" BEL "u_sru_trigger/u_trig_cnt/event_cnt_wr_en" BEL "u_sru_trigger/u_trig_cnt/stc" BEL "u_sru_trigger/u_trig_cnt/stb" BEL "u_sru_trigger/u_trig_cnt/stall_events" BEL "u_sru_trigger/u_trig_cnt/BusyFlag_d" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd4" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_15" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_14" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_13" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_12" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_11" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_10" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_9" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_8" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_7" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_6" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_5" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_4" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_3" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_2" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_1" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_0" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd1" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd2" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd3" BEL "u_sru_trigger/u_test_trig_gen/sta_FSM_FFd1" BEL "u_sru_trigger/u_test_trig_gen/sta_FSM_FFd2" BEL "u_sru_trigger/u_test_trig_gen/test_trig" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_15" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_14" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_13" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_12" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_11" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_10" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_9" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_8" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_7" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_6" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_5" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_4" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_3" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_2" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_1" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_0" BEL "u_sru_trigger/u_test_trig_gen/test_l0" BEL "u_sru_trigger/u_test_trig_gen/test_l2a" BEL "u_sru_trigger/u_test_trig_gen/test_l1" BEL "u_sru_trigger/u_test_trig_gen/l0_trig" BEL "u_sru_trigger/u_test_trig_gen/test_pulse" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd3" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_11" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_10" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_9" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_8" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_7" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_6" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_5" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_4" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_3" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_2" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_1" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_0" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd1" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd4" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd2" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd6" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd7" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd5" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd8" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd9" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd10" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd11" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd13" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd14" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd12" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd16" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd17" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd15" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd18" BEL "u_sru_trigger/u_trig_err_detect/DtcRamClr" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_20" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_19" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_18" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_17" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_16" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_15" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_13" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_11" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_9" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_8" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_7" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_6" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_5" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_4" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_3" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_2" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_1" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_0" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_15" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_14" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_13" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_12" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_11" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_10" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_9" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_8" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_7" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_6" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_5" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_4" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_3" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_2" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_1" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_0" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_5" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_2" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_1" BEL "u_sru_trigger/u_trig_err_detect/abortcmd_c" BEL "u_sru_trigger/u_trig_err_detect/rdocmd_c" BEL "u_sru_trigger/u_trig_err_detect/trig_busy" BEL "u_sru_trigger/u_trig_err_detect/ddl_tx_start_i" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_cmd_par/synch_dcs/o" BEL "u_sru_cmd_par/synch_dcs/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_40/Mshreg_o" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/last_packet_sync_ff_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/Mshreg_last_packet_sync_ff_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_d" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_39" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_38" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_37" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_36" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_35" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_34" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_33" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_32" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_31" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_30" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_29" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_28" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_27" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_26" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_25" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_24" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_23" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_22" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_21" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_20" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_19" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_18" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_17" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_16" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_15" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_14" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_13" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_12" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_11" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_10" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_9" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_8" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/last_packet_sync_ff_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_0" BEL "u_main_clk_gen/TrigIOClkSel" BEL "u_SCLKPhaseDetect/cnt_i_1" BEL "u_SCLKPhaseDetect/cnt_i_0" BEL "u_SCLKPhaseDetect/st_FSM_FFd1" BEL "u_SCLKPhaseDetect/st_FSM_FFd2" BEL "u_SCLKPhaseDetect/sclkphasecnt_1" BEL "u_SCLKPhaseDetect/sclkphasecnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/fifo_rd_en" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_dv" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_15" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_14" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_13" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_12" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_11" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_10" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_9" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_8" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_7" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_6" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_5" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_4" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_3" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_2" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_1" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_0" BEL "u_sru_cmd_par/u_ResetSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_ResetSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_ResetSwitch/pulse_out_i" BEL "u_sru_cmd_par/u_BusyClrSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_BusyClrSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_BusyClrSwitch/pulse_out_i" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/pulse_out_i" BEL "u_sru_cmd_par/usrudcsreplyack/st_FSM_FFd1" BEL "u_sru_cmd_par/usrudcsreplyack/st_FSM_FFd2" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_update" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_63" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_62" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_61" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_60" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_59" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_58" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_57" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_56" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_55" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_54" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_53" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_52" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_51" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_50" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_49" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_48" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_47" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_46" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_45" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_44" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_43" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_42" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_41" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_40" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_39" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_38" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_37" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_36" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_35" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_34" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_33" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_32" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_31" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_30" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_29" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_28" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_27" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_26" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_25" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_24" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_23" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_22" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_21" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_20" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_19" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_18" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_17" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_16" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_15" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_14" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_13" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_12" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_11" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_10" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_9" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_8" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_7" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_6" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_5" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_4" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_3" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_2" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_1" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_0" PIN "u_sru_cmd_par/u_srutempmonitor/SYSMON_INST_pins<10>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<65>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout4_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout3_0 = BEL "htrig_number_d" BEL "spill_sync_dd" BEL "u_sru_40dtc_top/DtcRamFlag_ii_39" BEL "u_sru_40dtc_top/DtcRamFlag_ii_38" BEL "u_sru_40dtc_top/DtcRamFlag_ii_37" BEL "u_sru_40dtc_top/DtcRamFlag_ii_36" BEL "u_sru_40dtc_top/DtcRamFlag_ii_35" BEL "u_sru_40dtc_top/DtcRamFlag_ii_34" BEL "u_sru_40dtc_top/DtcRamFlag_ii_33" BEL "u_sru_40dtc_top/DtcRamFlag_ii_32" BEL "u_sru_40dtc_top/DtcRamFlag_ii_31" BEL "u_sru_40dtc_top/DtcRamFlag_ii_30" BEL "u_sru_40dtc_top/DtcRamFlag_ii_29" BEL "u_sru_40dtc_top/DtcRamFlag_ii_28" BEL "u_sru_40dtc_top/DtcRamFlag_ii_27" BEL "u_sru_40dtc_top/DtcRamFlag_ii_26" BEL "u_sru_40dtc_top/DtcRamFlag_ii_25" BEL "u_sru_40dtc_top/DtcRamFlag_ii_24" BEL "u_sru_40dtc_top/DtcRamFlag_ii_23" BEL "u_sru_40dtc_top/DtcRamFlag_ii_22" BEL "u_sru_40dtc_top/DtcRamFlag_ii_21" BEL "u_sru_40dtc_top/DtcRamFlag_ii_20" BEL "u_sru_40dtc_top/DtcRamFlag_ii_19" BEL "u_sru_40dtc_top/DtcRamFlag_ii_18" BEL "u_sru_40dtc_top/DtcRamFlag_ii_17" BEL "u_sru_40dtc_top/DtcRamFlag_ii_16" BEL "u_sru_40dtc_top/DtcRamFlag_ii_15" BEL "u_sru_40dtc_top/DtcRamFlag_ii_14" BEL "u_sru_40dtc_top/DtcRamFlag_ii_13" BEL "u_sru_40dtc_top/DtcRamFlag_ii_12" BEL "u_sru_40dtc_top/DtcRamFlag_ii_11" BEL "u_sru_40dtc_top/DtcRamFlag_ii_10" BEL "u_sru_40dtc_top/DtcRamFlag_ii_9" BEL "u_sru_40dtc_top/DtcRamFlag_ii_8" BEL "u_sru_40dtc_top/DtcRamFlag_ii_7" BEL "u_sru_40dtc_top/DtcRamFlag_ii_6" BEL "u_sru_40dtc_top/DtcRamFlag_ii_5" BEL "u_sru_40dtc_top/DtcRamFlag_ii_4" BEL "u_sru_40dtc_top/DtcRamFlag_ii_3" BEL "u_sru_40dtc_top/DtcRamFlag_ii_2" BEL "u_sru_40dtc_top/DtcRamFlag_ii_1" BEL "u_sru_40dtc_top/DtcRamFlag_ii_0" BEL "u_sru_40dtc_top/abortcmd_i_39" BEL "u_sru_40dtc_top/abortcmd_i_38" BEL "u_sru_40dtc_top/abortcmd_i_37" BEL "u_sru_40dtc_top/abortcmd_i_36" BEL "u_sru_40dtc_top/abortcmd_i_35" BEL "u_sru_40dtc_top/abortcmd_i_34" BEL "u_sru_40dtc_top/abortcmd_i_33" BEL "u_sru_40dtc_top/abortcmd_i_32" BEL "u_sru_40dtc_top/abortcmd_i_31" BEL "u_sru_40dtc_top/abortcmd_i_30" BEL "u_sru_40dtc_top/abortcmd_i_29" BEL "u_sru_40dtc_top/abortcmd_i_28" BEL "u_sru_40dtc_top/abortcmd_i_27" BEL "u_sru_40dtc_top/abortcmd_i_26" BEL "u_sru_40dtc_top/abortcmd_i_25" BEL "u_sru_40dtc_top/abortcmd_i_24" BEL "u_sru_40dtc_top/abortcmd_i_23" BEL "u_sru_40dtc_top/abortcmd_i_22" BEL "u_sru_40dtc_top/abortcmd_i_21" BEL "u_sru_40dtc_top/abortcmd_i_20" BEL "u_sru_40dtc_top/abortcmd_i_19" BEL "u_sru_40dtc_top/abortcmd_i_18" BEL "u_sru_40dtc_top/abortcmd_i_17" BEL "u_sru_40dtc_top/abortcmd_i_16" BEL "u_sru_40dtc_top/abortcmd_i_15" BEL "u_sru_40dtc_top/abortcmd_i_14" BEL "u_sru_40dtc_top/abortcmd_i_13" BEL "u_sru_40dtc_top/abortcmd_i_12" BEL "u_sru_40dtc_top/abortcmd_i_11" BEL "u_sru_40dtc_top/abortcmd_i_10" BEL "u_sru_40dtc_top/abortcmd_i_9" BEL "u_sru_40dtc_top/abortcmd_i_8" BEL "u_sru_40dtc_top/abortcmd_i_7" BEL "u_sru_40dtc_top/abortcmd_i_6" BEL "u_sru_40dtc_top/abortcmd_i_5" BEL "u_sru_40dtc_top/abortcmd_i_4" BEL "u_sru_40dtc_top/abortcmd_i_3" BEL "u_sru_40dtc_top/abortcmd_i_2" BEL "u_sru_40dtc_top/abortcmd_i_1" BEL "u_sru_40dtc_top/abortcmd_i_0" BEL "u_sru_40dtc_top/DTCEventRdy_i_39" BEL "u_sru_40dtc_top/DTCEventRdy_i_38" BEL "u_sru_40dtc_top/DTCEventRdy_i_37" BEL "u_sru_40dtc_top/DTCEventRdy_i_36" BEL "u_sru_40dtc_top/DTCEventRdy_i_35" BEL "u_sru_40dtc_top/DTCEventRdy_i_34" BEL "u_sru_40dtc_top/DTCEventRdy_i_33" BEL "u_sru_40dtc_top/DTCEventRdy_i_32" BEL "u_sru_40dtc_top/DTCEventRdy_i_31" BEL "u_sru_40dtc_top/DTCEventRdy_i_30" BEL "u_sru_40dtc_top/DTCEventRdy_i_29" BEL "u_sru_40dtc_top/DTCEventRdy_i_28" BEL "u_sru_40dtc_top/DTCEventRdy_i_27" BEL "u_sru_40dtc_top/DTCEventRdy_i_26" BEL "u_sru_40dtc_top/DTCEventRdy_i_25" BEL "u_sru_40dtc_top/DTCEventRdy_i_24" BEL "u_sru_40dtc_top/DTCEventRdy_i_23" BEL "u_sru_40dtc_top/DTCEventRdy_i_22" BEL "u_sru_40dtc_top/DTCEventRdy_i_21" BEL "u_sru_40dtc_top/DTCEventRdy_i_20" BEL "u_sru_40dtc_top/DTCEventRdy_i_19" BEL "u_sru_40dtc_top/DTCEventRdy_i_18" BEL "u_sru_40dtc_top/DTCEventRdy_i_17" BEL "u_sru_40dtc_top/DTCEventRdy_i_16" BEL "u_sru_40dtc_top/DTCEventRdy_i_15" BEL "u_sru_40dtc_top/DTCEventRdy_i_14" BEL "u_sru_40dtc_top/DTCEventRdy_i_13" BEL "u_sru_40dtc_top/DTCEventRdy_i_12" BEL "u_sru_40dtc_top/DTCEventRdy_i_11" BEL "u_sru_40dtc_top/DTCEventRdy_i_10" BEL "u_sru_40dtc_top/DTCEventRdy_i_9" BEL "u_sru_40dtc_top/DTCEventRdy_i_8" BEL "u_sru_40dtc_top/DTCEventRdy_i_7" BEL "u_sru_40dtc_top/DTCEventRdy_i_6" BEL "u_sru_40dtc_top/DTCEventRdy_i_5" BEL "u_sru_40dtc_top/DTCEventRdy_i_4" BEL "u_sru_40dtc_top/DTCEventRdy_i_3" BEL "u_sru_40dtc_top/DTCEventRdy_i_2" BEL "u_sru_40dtc_top/DTCEventRdy_i_1" BEL "u_sru_40dtc_top/DTCEventRdy_i_0" BEL "u_sru_40dtc_top/FeeTrig_i_39" BEL "u_sru_40dtc_top/FeeTrig_i_38" BEL "u_sru_40dtc_top/FeeTrig_i_37" BEL "u_sru_40dtc_top/FeeTrig_i_36" BEL "u_sru_40dtc_top/FeeTrig_i_35" BEL "u_sru_40dtc_top/FeeTrig_i_34" BEL "u_sru_40dtc_top/FeeTrig_i_33" BEL "u_sru_40dtc_top/FeeTrig_i_32" BEL "u_sru_40dtc_top/FeeTrig_i_31" BEL "u_sru_40dtc_top/FeeTrig_i_30" BEL "u_sru_40dtc_top/FeeTrig_i_29" BEL "u_sru_40dtc_top/FeeTrig_i_28" BEL "u_sru_40dtc_top/FeeTrig_i_27" BEL "u_sru_40dtc_top/FeeTrig_i_26" BEL "u_sru_40dtc_top/FeeTrig_i_25" BEL "u_sru_40dtc_top/FeeTrig_i_24" BEL "u_sru_40dtc_top/FeeTrig_i_23" BEL "u_sru_40dtc_top/FeeTrig_i_22" BEL "u_sru_40dtc_top/FeeTrig_i_21" BEL "u_sru_40dtc_top/FeeTrig_i_20" BEL "u_sru_40dtc_top/FeeTrig_i_19" BEL "u_sru_40dtc_top/FeeTrig_i_18" BEL "u_sru_40dtc_top/FeeTrig_i_17" BEL "u_sru_40dtc_top/FeeTrig_i_16" BEL "u_sru_40dtc_top/FeeTrig_i_15" BEL "u_sru_40dtc_top/FeeTrig_i_14" BEL "u_sru_40dtc_top/FeeTrig_i_13" BEL "u_sru_40dtc_top/FeeTrig_i_12" BEL "u_sru_40dtc_top/FeeTrig_i_11" BEL "u_sru_40dtc_top/FeeTrig_i_10" BEL "u_sru_40dtc_top/FeeTrig_i_9" BEL "u_sru_40dtc_top/FeeTrig_i_8" BEL "u_sru_40dtc_top/FeeTrig_i_7" BEL "u_sru_40dtc_top/FeeTrig_i_6" BEL "u_sru_40dtc_top/FeeTrig_i_5" BEL "u_sru_40dtc_top/FeeTrig_i_4" BEL "u_sru_40dtc_top/FeeTrig_i_3" BEL "u_sru_40dtc_top/FeeTrig_i_2" BEL "u_sru_40dtc_top/FeeTrig_i_1" BEL "u_sru_40dtc_top/FeeTrig_i_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/clk_ODELAY" BEL "u_sru_cmd_par/BusyCnt_31" BEL "u_sru_cmd_par/BusyCnt_30" BEL "u_sru_cmd_par/BusyCnt_29" BEL "u_sru_cmd_par/BusyCnt_28" BEL "u_sru_cmd_par/BusyCnt_27" BEL "u_sru_cmd_par/BusyCnt_26" BEL "u_sru_cmd_par/BusyCnt_25" BEL "u_sru_cmd_par/BusyCnt_24" BEL "u_sru_cmd_par/BusyCnt_23" BEL "u_sru_cmd_par/BusyCnt_22" BEL "u_sru_cmd_par/BusyCnt_21" BEL "u_sru_cmd_par/BusyCnt_20" BEL "u_sru_cmd_par/BusyCnt_19" BEL "u_sru_cmd_par/BusyCnt_18" BEL "u_sru_cmd_par/BusyCnt_17" BEL "u_sru_cmd_par/BusyCnt_16" BEL "u_sru_cmd_par/BusyCnt_15" BEL "u_sru_cmd_par/BusyCnt_14" BEL "u_sru_cmd_par/BusyCnt_13" BEL "u_sru_cmd_par/BusyCnt_12" BEL "u_sru_cmd_par/BusyCnt_11" BEL "u_sru_cmd_par/BusyCnt_10" BEL "u_sru_cmd_par/BusyCnt_9" BEL "u_sru_cmd_par/BusyCnt_8" BEL "u_sru_cmd_par/BusyCnt_7" BEL "u_sru_cmd_par/BusyCnt_6" BEL "u_sru_cmd_par/BusyCnt_5" BEL "u_sru_cmd_par/BusyCnt_4" BEL "u_sru_cmd_par/BusyCnt_3" BEL "u_sru_cmd_par/BusyCnt_2" BEL "u_sru_cmd_par/BusyCnt_1" BEL "u_sru_cmd_par/BusyCnt_0" BEL "u_sru_cmd_par/SRUMonData_15" BEL "u_sru_cmd_par/SRUMonData_14" BEL "u_sru_cmd_par/SRUMonData_13" BEL "u_sru_cmd_par/SRUMonData_12" BEL "u_sru_cmd_par/SRUMonData_11" BEL "u_sru_cmd_par/SRUMonData_10" BEL "u_sru_cmd_par/SRUMonData_9" BEL "u_sru_cmd_par/SRUMonData_8" BEL "u_sru_cmd_par/SRUMonData_7" BEL "u_sru_cmd_par/SRUMonData_6" BEL "u_sru_cmd_par/SRUMonData_5" BEL "u_sru_cmd_par/SRUMonData_4" BEL "u_sru_cmd_par/SRUMonData_3" BEL "u_sru_cmd_par/SRUMonData_2" BEL "u_sru_cmd_par/SRUMonData_1" BEL "u_sru_cmd_par/SRUMonData_0" BEL "u_sru_cmd_par/FastCmdCode_7" BEL "u_sru_cmd_par/FastCmdCode_6" BEL "u_sru_cmd_par/FastCmdCode_5" BEL "u_sru_cmd_par/FastCmdCode_4" BEL "u_sru_cmd_par/FastCmdCode_3" BEL "u_sru_cmd_par/FastCmdCode_2" BEL "u_sru_cmd_par/FastCmdCode_1" BEL "u_sru_cmd_par/FastCmdCode_0" BEL "u_sru_cmd_par/walign_reg_31" BEL "u_sru_cmd_par/walign_reg_30" BEL "u_sru_cmd_par/walign_reg_29" BEL "u_sru_cmd_par/walign_reg_28" BEL "u_sru_cmd_par/walign_reg_27" BEL "u_sru_cmd_par/walign_reg_26" BEL "u_sru_cmd_par/walign_reg_25" BEL "u_sru_cmd_par/walign_reg_24" BEL "u_sru_cmd_par/walign_reg_23" BEL "u_sru_cmd_par/walign_reg_22" BEL "u_sru_cmd_par/walign_reg_21" BEL "u_sru_cmd_par/walign_reg_20" BEL "u_sru_cmd_par/walign_reg_19" BEL "u_sru_cmd_par/walign_reg_18" BEL "u_sru_cmd_par/walign_reg_17" BEL "u_sru_cmd_par/walign_reg_16" BEL "u_sru_cmd_par/walign_reg_15" BEL "u_sru_cmd_par/walign_reg_14" BEL "u_sru_cmd_par/walign_reg_13" BEL "u_sru_cmd_par/walign_reg_12" BEL "u_sru_cmd_par/walign_reg_11" BEL "u_sru_cmd_par/walign_reg_10" BEL "u_sru_cmd_par/walign_reg_9" BEL "u_sru_cmd_par/walign_reg_8" BEL "u_sru_cmd_par/walign_reg_7" BEL "u_sru_cmd_par/walign_reg_6" BEL "u_sru_cmd_par/walign_reg_5" BEL "u_sru_cmd_par/walign_reg_4" BEL "u_sru_cmd_par/walign_reg_3" BEL "u_sru_cmd_par/walign_reg_2" BEL "u_sru_cmd_par/walign_reg_1" BEL "u_sru_cmd_par/walign_reg_0" BEL "u_sru_cmd_par/errtest_reg_31" BEL "u_sru_cmd_par/errtest_reg_30" BEL "u_sru_cmd_par/errtest_reg_29" BEL "u_sru_cmd_par/errtest_reg_28" BEL "u_sru_cmd_par/errtest_reg_27" BEL "u_sru_cmd_par/errtest_reg_26" BEL "u_sru_cmd_par/errtest_reg_25" BEL "u_sru_cmd_par/errtest_reg_24" BEL "u_sru_cmd_par/errtest_reg_23" BEL "u_sru_cmd_par/errtest_reg_22" BEL "u_sru_cmd_par/errtest_reg_21" BEL "u_sru_cmd_par/errtest_reg_20" BEL "u_sru_cmd_par/errtest_reg_19" BEL "u_sru_cmd_par/errtest_reg_18" BEL "u_sru_cmd_par/errtest_reg_17" BEL "u_sru_cmd_par/errtest_reg_16" BEL "u_sru_cmd_par/errtest_reg_15" BEL "u_sru_cmd_par/errtest_reg_14" BEL "u_sru_cmd_par/errtest_reg_13" BEL "u_sru_cmd_par/errtest_reg_12" BEL "u_sru_cmd_par/errtest_reg_11" BEL "u_sru_cmd_par/errtest_reg_10" BEL "u_sru_cmd_par/errtest_reg_9" BEL "u_sru_cmd_par/errtest_reg_8" BEL "u_sru_cmd_par/errtest_reg_7" BEL "u_sru_cmd_par/errtest_reg_6" BEL "u_sru_cmd_par/errtest_reg_5" BEL "u_sru_cmd_par/errtest_reg_4" BEL "u_sru_cmd_par/errtest_reg_3" BEL "u_sru_cmd_par/errtest_reg_2" BEL "u_sru_cmd_par/errtest_reg_1" BEL "u_sru_cmd_par/errtest_reg_0" BEL "u_sru_cmd_par/FastCmd_reg_15" BEL "u_sru_cmd_par/FastCmd_reg_14" BEL "u_sru_cmd_par/FastCmd_reg_13" BEL "u_sru_cmd_par/FastCmd_reg_12" BEL "u_sru_cmd_par/FastCmd_reg_11" BEL "u_sru_cmd_par/FastCmd_reg_10" BEL "u_sru_cmd_par/FastCmd_reg_9" BEL "u_sru_cmd_par/FastCmd_reg_8" BEL "u_sru_cmd_par/FastCmd_reg_7" BEL "u_sru_cmd_par/FastCmd_reg_6" BEL "u_sru_cmd_par/FastCmd_reg_5" BEL "u_sru_cmd_par/FastCmd_reg_4" BEL "u_sru_cmd_par/FastCmd_reg_3" BEL "u_sru_cmd_par/FastCmd_reg_2" BEL "u_sru_cmd_par/FastCmd_reg_1" BEL "u_sru_cmd_par/FastCmd_reg_0" BEL "u_sru_cmd_par/dtc_out_phase_cmd" BEL "u_sru_cmd_par/event_countdown_wr_en" BEL "u_sru_cmd_par/timestamp_clr" BEL "u_sru_cmd_par/busyclr_cmd" BEL "u_sru_cmd_par/trigerr_clr" BEL "u_sru_cmd_par/trigcnt_clr" BEL "u_sru_cmd_par/evnt_clr" BEL "u_sru_cmd_par/pscmd" BEL "u_sru_cmd_par/strig_cmd" BEL "u_sru_cmd_par/FPGAReload_i" BEL "u_sru_cmd_par/errtest_cmd" BEL "u_sru_cmd_par/walign_cmd" BEL "u_sru_cmd_par/test_pulse_width_9" BEL "u_sru_cmd_par/test_pulse_width_8" BEL "u_sru_cmd_par/test_pulse_width_7" BEL "u_sru_cmd_par/test_pulse_width_6" BEL "u_sru_cmd_par/test_pulse_width_5" BEL "u_sru_cmd_par/test_pulse_width_4" BEL "u_sru_cmd_par/test_pulse_width_3" BEL "u_sru_cmd_par/test_pulse_width_2" BEL "u_sru_cmd_par/test_pulse_width_1" BEL "u_sru_cmd_par/test_pulse_width_0" BEL "u_sru_cmd_par/testtrigcfg1_31" BEL "u_sru_cmd_par/testtrigcfg1_30" BEL "u_sru_cmd_par/testtrigcfg1_29" BEL "u_sru_cmd_par/testtrigcfg1_28" BEL "u_sru_cmd_par/testtrigcfg1_27" BEL "u_sru_cmd_par/testtrigcfg1_26" BEL "u_sru_cmd_par/testtrigcfg1_25" BEL "u_sru_cmd_par/testtrigcfg1_24" BEL "u_sru_cmd_par/testtrigcfg1_23" BEL "u_sru_cmd_par/testtrigcfg1_22" BEL "u_sru_cmd_par/testtrigcfg1_21" BEL "u_sru_cmd_par/testtrigcfg1_20" BEL "u_sru_cmd_par/testtrigcfg1_19" BEL "u_sru_cmd_par/testtrigcfg1_18" BEL "u_sru_cmd_par/testtrigcfg1_17" BEL "u_sru_cmd_par/testtrigcfg1_16" BEL "u_sru_cmd_par/testtrigcfg1_15" BEL "u_sru_cmd_par/testtrigcfg1_14" BEL "u_sru_cmd_par/testtrigcfg1_13" BEL "u_sru_cmd_par/testtrigcfg1_12" BEL "u_sru_cmd_par/testtrigcfg1_11" BEL "u_sru_cmd_par/testtrigcfg1_10" BEL "u_sru_cmd_par/testtrigcfg1_9" BEL "u_sru_cmd_par/testtrigcfg1_8" BEL "u_sru_cmd_par/testtrigcfg1_7" BEL "u_sru_cmd_par/testtrigcfg1_6" BEL "u_sru_cmd_par/testtrigcfg1_5" BEL "u_sru_cmd_par/testtrigcfg1_4" BEL "u_sru_cmd_par/testtrigcfg1_3" BEL "u_sru_cmd_par/testtrigcfg1_2" BEL "u_sru_cmd_par/testtrigcfg1_1" BEL "u_sru_cmd_par/testtrigcfg1_0" BEL "u_sru_cmd_par/test_pulse_start_15" BEL "u_sru_cmd_par/test_pulse_start_14" BEL "u_sru_cmd_par/test_pulse_start_13" BEL "u_sru_cmd_par/test_pulse_start_12" BEL "u_sru_cmd_par/test_pulse_start_11" BEL "u_sru_cmd_par/test_pulse_start_10" BEL "u_sru_cmd_par/test_pulse_start_9" BEL "u_sru_cmd_par/test_pulse_start_8" BEL "u_sru_cmd_par/test_pulse_start_7" BEL "u_sru_cmd_par/test_pulse_start_6" BEL "u_sru_cmd_par/test_pulse_start_5" BEL "u_sru_cmd_par/test_pulse_start_4" BEL "u_sru_cmd_par/test_pulse_start_3" BEL "u_sru_cmd_par/test_pulse_start_2" BEL "u_sru_cmd_par/test_pulse_start_1" BEL "u_sru_cmd_par/test_pulse_start_0" BEL "u_sru_cmd_par/ptrigcfg_16" BEL "u_sru_cmd_par/ptrigcfg_15" BEL "u_sru_cmd_par/ptrigcfg_14" BEL "u_sru_cmd_par/ptrigcfg_13" BEL "u_sru_cmd_par/ptrigcfg_12" BEL "u_sru_cmd_par/ptrigcfg_11" BEL "u_sru_cmd_par/ptrigcfg_10" BEL "u_sru_cmd_par/ptrigcfg_9" BEL "u_sru_cmd_par/ptrigcfg_8" BEL "u_sru_cmd_par/ptrigcfg_7" BEL "u_sru_cmd_par/ptrigcfg_6" BEL "u_sru_cmd_par/ptrigcfg_5" BEL "u_sru_cmd_par/ptrigcfg_4" BEL "u_sru_cmd_par/ptrigcfg_3" BEL "u_sru_cmd_par/ptrigcfg_2" BEL "u_sru_cmd_par/ptrigcfg_1" BEL "u_sru_cmd_par/ptrigcfg_0" BEL "u_sru_cmd_par/trigl2tw_31" BEL "u_sru_cmd_par/trigl2tw_30" BEL "u_sru_cmd_par/trigl2tw_29" BEL "u_sru_cmd_par/trigl2tw_28" BEL "u_sru_cmd_par/trigl2tw_27" BEL "u_sru_cmd_par/trigl2tw_26" BEL "u_sru_cmd_par/trigl2tw_25" BEL "u_sru_cmd_par/trigl2tw_24" BEL "u_sru_cmd_par/trigl2tw_23" BEL "u_sru_cmd_par/trigl2tw_22" BEL "u_sru_cmd_par/trigl2tw_21" BEL "u_sru_cmd_par/trigl2tw_20" BEL "u_sru_cmd_par/trigl2tw_19" BEL "u_sru_cmd_par/trigl2tw_18" BEL "u_sru_cmd_par/trigl2tw_17" BEL "u_sru_cmd_par/trigl2tw_16" BEL "u_sru_cmd_par/trigl2tw_15" BEL "u_sru_cmd_par/trigl2tw_14" BEL "u_sru_cmd_par/trigl2tw_13" BEL "u_sru_cmd_par/trigl2tw_12" BEL "u_sru_cmd_par/trigl2tw_11" BEL "u_sru_cmd_par/trigl2tw_10" BEL "u_sru_cmd_par/trigl2tw_9" BEL "u_sru_cmd_par/trigl2tw_8" BEL "u_sru_cmd_par/trigl2tw_7" BEL "u_sru_cmd_par/trigl2tw_6" BEL "u_sru_cmd_par/trigl2tw_5" BEL "u_sru_cmd_par/trigl2tw_4" BEL "u_sru_cmd_par/trigl2tw_3" BEL "u_sru_cmd_par/trigl2tw_2" BEL "u_sru_cmd_par/trigl2tw_1" BEL "u_sru_cmd_par/trigl2tw_0" BEL "u_sru_cmd_par/testtrigcfg0_31" BEL "u_sru_cmd_par/testtrigcfg0_30" BEL "u_sru_cmd_par/testtrigcfg0_29" BEL "u_sru_cmd_par/testtrigcfg0_28" BEL "u_sru_cmd_par/testtrigcfg0_27" BEL "u_sru_cmd_par/testtrigcfg0_26" BEL "u_sru_cmd_par/testtrigcfg0_25" BEL "u_sru_cmd_par/testtrigcfg0_24" BEL "u_sru_cmd_par/testtrigcfg0_23" BEL "u_sru_cmd_par/testtrigcfg0_22" BEL "u_sru_cmd_par/testtrigcfg0_21" BEL "u_sru_cmd_par/testtrigcfg0_20" BEL "u_sru_cmd_par/testtrigcfg0_19" BEL "u_sru_cmd_par/testtrigcfg0_18" BEL "u_sru_cmd_par/testtrigcfg0_17" BEL "u_sru_cmd_par/testtrigcfg0_16" BEL "u_sru_cmd_par/testtrigcfg0_15" BEL "u_sru_cmd_par/testtrigcfg0_14" BEL "u_sru_cmd_par/testtrigcfg0_13" BEL "u_sru_cmd_par/testtrigcfg0_12" BEL "u_sru_cmd_par/testtrigcfg0_11" BEL "u_sru_cmd_par/testtrigcfg0_10" BEL "u_sru_cmd_par/testtrigcfg0_9" BEL "u_sru_cmd_par/testtrigcfg0_8" BEL "u_sru_cmd_par/testtrigcfg0_7" BEL "u_sru_cmd_par/testtrigcfg0_6" BEL "u_sru_cmd_par/testtrigcfg0_5" BEL "u_sru_cmd_par/testtrigcfg0_4" BEL "u_sru_cmd_par/testtrigcfg0_3" BEL "u_sru_cmd_par/testtrigcfg0_2" BEL "u_sru_cmd_par/testtrigcfg0_1" BEL "u_sru_cmd_par/testtrigcfg0_0" BEL "u_sru_cmd_par/trigl1tw_31" BEL "u_sru_cmd_par/trigl1tw_30" BEL "u_sru_cmd_par/trigl1tw_29" BEL "u_sru_cmd_par/trigl1tw_28" BEL "u_sru_cmd_par/trigl1tw_27" BEL "u_sru_cmd_par/trigl1tw_26" BEL "u_sru_cmd_par/trigl1tw_25" BEL "u_sru_cmd_par/trigl1tw_24" BEL "u_sru_cmd_par/trigl1tw_23" BEL "u_sru_cmd_par/trigl1tw_22" BEL "u_sru_cmd_par/trigl1tw_21" BEL "u_sru_cmd_par/trigl1tw_20" BEL "u_sru_cmd_par/trigl1tw_19" BEL "u_sru_cmd_par/trigl1tw_18" BEL "u_sru_cmd_par/trigl1tw_17" BEL "u_sru_cmd_par/trigl1tw_16" BEL "u_sru_cmd_par/trigl1tw_15" BEL "u_sru_cmd_par/trigl1tw_14" BEL "u_sru_cmd_par/trigl1tw_13" BEL "u_sru_cmd_par/trigl1tw_12" BEL "u_sru_cmd_par/trigl1tw_11" BEL "u_sru_cmd_par/trigl1tw_10" BEL "u_sru_cmd_par/trigl1tw_9" BEL "u_sru_cmd_par/trigl1tw_8" BEL "u_sru_cmd_par/trigl1tw_7" BEL "u_sru_cmd_par/trigl1tw_6" BEL "u_sru_cmd_par/trigl1tw_5" BEL "u_sru_cmd_par/trigl1tw_4" BEL "u_sru_cmd_par/trigl1tw_3" BEL "u_sru_cmd_par/trigl1tw_2" BEL "u_sru_cmd_par/trigl1tw_1" BEL "u_sru_cmd_par/trigl1tw_0" BEL "u_sru_cmd_par/psscancfg_16" BEL "u_sru_cmd_par/psscancfg_15" BEL "u_sru_cmd_par/psscancfg_14" BEL "u_sru_cmd_par/psscancfg_13" BEL "u_sru_cmd_par/psscancfg_12" BEL "u_sru_cmd_par/psscancfg_11" BEL "u_sru_cmd_par/psscancfg_10" BEL "u_sru_cmd_par/psscancfg_9" BEL "u_sru_cmd_par/psscancfg_8" BEL "u_sru_cmd_par/psscancfg_7" BEL "u_sru_cmd_par/psscancfg_6" BEL "u_sru_cmd_par/psscancfg_5" BEL "u_sru_cmd_par/psscancfg_4" BEL "u_sru_cmd_par/psscancfg_3" BEL "u_sru_cmd_par/psscancfg_2" BEL "u_sru_cmd_par/psscancfg_1" BEL "u_sru_cmd_par/psscancfg_0" BEL "u_sru_cmd_par/dtc_power_en_39" BEL "u_sru_cmd_par/dtc_power_en_38" BEL "u_sru_cmd_par/dtc_power_en_37" BEL "u_sru_cmd_par/dtc_power_en_36" BEL "u_sru_cmd_par/dtc_power_en_35" BEL "u_sru_cmd_par/dtc_power_en_34" BEL "u_sru_cmd_par/dtc_power_en_33" BEL "u_sru_cmd_par/dtc_power_en_32" BEL "u_sru_cmd_par/dtc_power_en_31" BEL "u_sru_cmd_par/dtc_power_en_30" BEL "u_sru_cmd_par/dtc_power_en_29" BEL "u_sru_cmd_par/dtc_power_en_28" BEL "u_sru_cmd_par/dtc_power_en_27" BEL "u_sru_cmd_par/dtc_power_en_26" BEL "u_sru_cmd_par/dtc_power_en_25" BEL "u_sru_cmd_par/dtc_power_en_24" BEL "u_sru_cmd_par/dtc_power_en_23" BEL "u_sru_cmd_par/dtc_power_en_22" BEL "u_sru_cmd_par/dtc_power_en_21" BEL "u_sru_cmd_par/dtc_power_en_20" BEL "u_sru_cmd_par/dtc_power_en_19" BEL "u_sru_cmd_par/dtc_power_en_18" BEL "u_sru_cmd_par/dtc_power_en_17" BEL "u_sru_cmd_par/dtc_power_en_16" BEL "u_sru_cmd_par/dtc_power_en_15" BEL "u_sru_cmd_par/dtc_power_en_14" BEL "u_sru_cmd_par/dtc_power_en_13" BEL "u_sru_cmd_par/dtc_power_en_12" BEL "u_sru_cmd_par/dtc_power_en_11" BEL "u_sru_cmd_par/dtc_power_en_10" BEL "u_sru_cmd_par/dtc_power_en_9" BEL "u_sru_cmd_par/dtc_power_en_8" BEL "u_sru_cmd_par/dtc_power_en_7" BEL "u_sru_cmd_par/dtc_power_en_6" BEL "u_sru_cmd_par/dtc_power_en_5" BEL "u_sru_cmd_par/dtc_power_en_4" BEL "u_sru_cmd_par/dtc_power_en_3" BEL "u_sru_cmd_par/dtc_power_en_2" BEL "u_sru_cmd_par/dtc_power_en_1" BEL "u_sru_cmd_par/dtc_power_en_0" BEL "u_sru_cmd_par/dtc_out_phase_delay_4" BEL "u_sru_cmd_par/dtc_out_phase_delay_3" BEL "u_sru_cmd_par/dtc_out_phase_delay_2" BEL "u_sru_cmd_par/dtc_out_phase_delay_1" BEL "u_sru_cmd_par/dtc_out_phase_delay_0" BEL "u_sru_cmd_par/dtc_out_phase_channel_5" BEL "u_sru_cmd_par/dtc_out_phase_channel_4" BEL "u_sru_cmd_par/dtc_out_phase_channel_3" BEL "u_sru_cmd_par/dtc_out_phase_channel_2" BEL "u_sru_cmd_par/dtc_out_phase_channel_1" BEL "u_sru_cmd_par/dtc_out_phase_channel_0" BEL "u_sru_cmd_par/event_countdown_input_31" BEL "u_sru_cmd_par/event_countdown_input_30" BEL "u_sru_cmd_par/event_countdown_input_29" BEL "u_sru_cmd_par/event_countdown_input_28" BEL "u_sru_cmd_par/event_countdown_input_27" BEL "u_sru_cmd_par/event_countdown_input_26" BEL "u_sru_cmd_par/event_countdown_input_25" BEL "u_sru_cmd_par/event_countdown_input_24" BEL "u_sru_cmd_par/event_countdown_input_23" BEL "u_sru_cmd_par/event_countdown_input_22" BEL "u_sru_cmd_par/event_countdown_input_21" BEL "u_sru_cmd_par/event_countdown_input_20" BEL "u_sru_cmd_par/event_countdown_input_19" BEL "u_sru_cmd_par/event_countdown_input_18" BEL "u_sru_cmd_par/event_countdown_input_17" BEL "u_sru_cmd_par/event_countdown_input_16" BEL "u_sru_cmd_par/event_countdown_input_15" BEL "u_sru_cmd_par/event_countdown_input_14" BEL "u_sru_cmd_par/event_countdown_input_13" BEL "u_sru_cmd_par/event_countdown_input_12" BEL "u_sru_cmd_par/event_countdown_input_11" BEL "u_sru_cmd_par/event_countdown_input_10" BEL "u_sru_cmd_par/event_countdown_input_9" BEL "u_sru_cmd_par/event_countdown_input_8" BEL "u_sru_cmd_par/event_countdown_input_7" BEL "u_sru_cmd_par/event_countdown_input_6" BEL "u_sru_cmd_par/event_countdown_input_5" BEL "u_sru_cmd_par/event_countdown_input_4" BEL "u_sru_cmd_par/event_countdown_input_3" BEL "u_sru_cmd_par/event_countdown_input_2" BEL "u_sru_cmd_par/event_countdown_input_1" BEL "u_sru_cmd_par/event_countdown_input_0" BEL "u_sru_cmd_par/dtc_mon_sel_5" BEL "u_sru_cmd_par/dtc_mon_sel_4" BEL "u_sru_cmd_par/dtc_mon_sel_3" BEL "u_sru_cmd_par/dtc_mon_sel_2" BEL "u_sru_cmd_par/dtc_mon_sel_1" BEL "u_sru_cmd_par/dtc_mon_sel_0" BEL "u_sru_cmd_par/readout_ip_31" BEL "u_sru_cmd_par/readout_ip_30" BEL "u_sru_cmd_par/readout_ip_29" BEL "u_sru_cmd_par/readout_ip_28" BEL "u_sru_cmd_par/readout_ip_27" BEL "u_sru_cmd_par/readout_ip_26" BEL "u_sru_cmd_par/readout_ip_25" BEL "u_sru_cmd_par/readout_ip_24" BEL "u_sru_cmd_par/readout_ip_23" BEL "u_sru_cmd_par/readout_ip_22" BEL "u_sru_cmd_par/readout_ip_21" BEL "u_sru_cmd_par/readout_ip_20" BEL "u_sru_cmd_par/readout_ip_19" BEL "u_sru_cmd_par/readout_ip_18" BEL "u_sru_cmd_par/readout_ip_17" BEL "u_sru_cmd_par/readout_ip_16" BEL "u_sru_cmd_par/readout_ip_15" BEL "u_sru_cmd_par/readout_ip_14" BEL "u_sru_cmd_par/readout_ip_13" BEL "u_sru_cmd_par/readout_ip_12" BEL "u_sru_cmd_par/readout_ip_11" BEL "u_sru_cmd_par/readout_ip_10" BEL "u_sru_cmd_par/readout_ip_9" BEL "u_sru_cmd_par/readout_ip_8" BEL "u_sru_cmd_par/readout_ip_7" BEL "u_sru_cmd_par/readout_ip_6" BEL "u_sru_cmd_par/readout_ip_5" BEL "u_sru_cmd_par/readout_ip_4" BEL "u_sru_cmd_par/readout_ip_3" BEL "u_sru_cmd_par/readout_ip_2" BEL "u_sru_cmd_par/readout_ip_1" BEL "u_sru_cmd_par/readout_ip_0" BEL "u_sru_cmd_par/SruMonAddr_6" BEL "u_sru_cmd_par/SruMonAddr_5" BEL "u_sru_cmd_par/SruMonAddr_4" BEL "u_sru_cmd_par/SruMonAddr_3" BEL "u_sru_cmd_par/SruMonAddr_2" BEL "u_sru_cmd_par/SruMonAddr_1" BEL "u_sru_cmd_par/SruMonAddr_0" BEL "u_sru_cmd_par/srucfg_31" BEL "u_sru_cmd_par/srucfg_30" BEL "u_sru_cmd_par/srucfg_29" BEL "u_sru_cmd_par/srucfg_28" BEL "u_sru_cmd_par/srucfg_27" BEL "u_sru_cmd_par/srucfg_26" BEL "u_sru_cmd_par/srucfg_25" BEL "u_sru_cmd_par/srucfg_24" BEL "u_sru_cmd_par/srucfg_23" BEL "u_sru_cmd_par/srucfg_22" BEL "u_sru_cmd_par/srucfg_21" BEL "u_sru_cmd_par/srucfg_20" BEL "u_sru_cmd_par/srucfg_19" BEL "u_sru_cmd_par/srucfg_18" BEL "u_sru_cmd_par/srucfg_17" BEL "u_sru_cmd_par/srucfg_16" BEL "u_sru_cmd_par/srucfg_15" BEL "u_sru_cmd_par/srucfg_14" BEL "u_sru_cmd_par/srucfg_13" BEL "u_sru_cmd_par/srucfg_12" BEL "u_sru_cmd_par/srucfg_11" BEL "u_sru_cmd_par/srucfg_10" BEL "u_sru_cmd_par/srucfg_9" BEL "u_sru_cmd_par/srucfg_8" BEL "u_sru_cmd_par/srucfg_7" BEL "u_sru_cmd_par/srucfg_6" BEL "u_sru_cmd_par/srucfg_5" BEL "u_sru_cmd_par/srucfg_4" BEL "u_sru_cmd_par/srucfg_3" BEL "u_sru_cmd_par/srucfg_2" BEL "u_sru_cmd_par/srucfg_1" BEL "u_sru_cmd_par/srucfg_0" BEL "u_sru_cmd_par/altrocfg_39" BEL "u_sru_cmd_par/altrocfg_38" BEL "u_sru_cmd_par/altrocfg_37" BEL "u_sru_cmd_par/altrocfg_36" BEL "u_sru_cmd_par/altrocfg_35" BEL "u_sru_cmd_par/altrocfg_34" BEL "u_sru_cmd_par/altrocfg_33" BEL "u_sru_cmd_par/altrocfg_32" BEL "u_sru_cmd_par/altrocfg_31" BEL "u_sru_cmd_par/altrocfg_30" BEL "u_sru_cmd_par/altrocfg_29" BEL "u_sru_cmd_par/altrocfg_28" BEL "u_sru_cmd_par/altrocfg_27" BEL "u_sru_cmd_par/altrocfg_26" BEL "u_sru_cmd_par/altrocfg_25" BEL "u_sru_cmd_par/altrocfg_24" BEL "u_sru_cmd_par/altrocfg_23" BEL "u_sru_cmd_par/altrocfg_22" BEL "u_sru_cmd_par/altrocfg_21" BEL "u_sru_cmd_par/altrocfg_20" BEL "u_sru_cmd_par/altrocfg_19" BEL "u_sru_cmd_par/altrocfg_18" BEL "u_sru_cmd_par/altrocfg_17" BEL "u_sru_cmd_par/altrocfg_16" BEL "u_sru_cmd_par/altrocfg_15" BEL "u_sru_cmd_par/altrocfg_14" BEL "u_sru_cmd_par/altrocfg_13" BEL "u_sru_cmd_par/altrocfg_12" BEL "u_sru_cmd_par/altrocfg_11" BEL "u_sru_cmd_par/altrocfg_10" BEL "u_sru_cmd_par/altrocfg_9" BEL "u_sru_cmd_par/altrocfg_8" BEL "u_sru_cmd_par/altrocfg_7" BEL "u_sru_cmd_par/altrocfg_6" BEL "u_sru_cmd_par/altrocfg_5" BEL "u_sru_cmd_par/altrocfg_4" BEL "u_sru_cmd_par/altrocfg_3" BEL "u_sru_cmd_par/altrocfg_2" BEL "u_sru_cmd_par/altrocfg_1" BEL "u_sru_cmd_par/altrocfg_0" BEL "u_sru_cmd_par/dtc_rdo_mask_i_39" BEL "u_sru_cmd_par/dtc_rdo_mask_i_38" BEL "u_sru_cmd_par/dtc_rdo_mask_i_37" BEL "u_sru_cmd_par/dtc_rdo_mask_i_36" BEL "u_sru_cmd_par/dtc_rdo_mask_i_35" BEL "u_sru_cmd_par/dtc_rdo_mask_i_34" BEL "u_sru_cmd_par/dtc_rdo_mask_i_33" BEL "u_sru_cmd_par/dtc_rdo_mask_i_32" BEL "u_sru_cmd_par/dtc_rdo_mask_i_31" BEL "u_sru_cmd_par/dtc_rdo_mask_i_30" BEL "u_sru_cmd_par/dtc_rdo_mask_i_29" BEL "u_sru_cmd_par/dtc_rdo_mask_i_28" BEL "u_sru_cmd_par/dtc_rdo_mask_i_27" BEL "u_sru_cmd_par/dtc_rdo_mask_i_26" BEL "u_sru_cmd_par/dtc_rdo_mask_i_25" BEL "u_sru_cmd_par/dtc_rdo_mask_i_24" BEL "u_sru_cmd_par/dtc_rdo_mask_i_23" BEL "u_sru_cmd_par/dtc_rdo_mask_i_22" BEL "u_sru_cmd_par/dtc_rdo_mask_i_21" BEL "u_sru_cmd_par/dtc_rdo_mask_i_20" BEL "u_sru_cmd_par/dtc_rdo_mask_i_19" BEL "u_sru_cmd_par/dtc_rdo_mask_i_18" BEL "u_sru_cmd_par/dtc_rdo_mask_i_17" BEL "u_sru_cmd_par/dtc_rdo_mask_i_16" BEL "u_sru_cmd_par/dtc_rdo_mask_i_15" BEL "u_sru_cmd_par/dtc_rdo_mask_i_14" BEL "u_sru_cmd_par/dtc_rdo_mask_i_13" BEL "u_sru_cmd_par/dtc_rdo_mask_i_12" BEL "u_sru_cmd_par/dtc_rdo_mask_i_11" BEL "u_sru_cmd_par/dtc_rdo_mask_i_10" BEL "u_sru_cmd_par/dtc_rdo_mask_i_9" BEL "u_sru_cmd_par/dtc_rdo_mask_i_8" BEL "u_sru_cmd_par/dtc_rdo_mask_i_7" BEL "u_sru_cmd_par/dtc_rdo_mask_i_6" BEL "u_sru_cmd_par/dtc_rdo_mask_i_5" BEL "u_sru_cmd_par/dtc_rdo_mask_i_4" BEL "u_sru_cmd_par/dtc_rdo_mask_i_3" BEL "u_sru_cmd_par/dtc_rdo_mask_i_2" BEL "u_sru_cmd_par/dtc_rdo_mask_i_1" BEL "u_sru_cmd_par/dtc_rdo_mask_i_0" BEL "u_sru_cmd_par/rcmd_reply_dv" BEL "u_sru_cmd_par/rcmd_reply_data_31" BEL "u_sru_cmd_par/rcmd_reply_data_30" BEL "u_sru_cmd_par/rcmd_reply_data_29" BEL "u_sru_cmd_par/rcmd_reply_data_28" BEL "u_sru_cmd_par/rcmd_reply_data_27" BEL "u_sru_cmd_par/rcmd_reply_data_26" BEL "u_sru_cmd_par/rcmd_reply_data_25" BEL "u_sru_cmd_par/rcmd_reply_data_24" BEL "u_sru_cmd_par/rcmd_reply_data_23" BEL "u_sru_cmd_par/rcmd_reply_data_22" BEL "u_sru_cmd_par/rcmd_reply_data_21" BEL "u_sru_cmd_par/rcmd_reply_data_20" BEL "u_sru_cmd_par/rcmd_reply_data_19" BEL "u_sru_cmd_par/rcmd_reply_data_18" BEL "u_sru_cmd_par/rcmd_reply_data_17" BEL "u_sru_cmd_par/rcmd_reply_data_16" BEL "u_sru_cmd_par/rcmd_reply_data_15" BEL "u_sru_cmd_par/rcmd_reply_data_14" BEL "u_sru_cmd_par/rcmd_reply_data_13" BEL "u_sru_cmd_par/rcmd_reply_data_12" BEL "u_sru_cmd_par/rcmd_reply_data_11" BEL "u_sru_cmd_par/rcmd_reply_data_10" BEL "u_sru_cmd_par/rcmd_reply_data_9" BEL "u_sru_cmd_par/rcmd_reply_data_8" BEL "u_sru_cmd_par/rcmd_reply_data_7" BEL "u_sru_cmd_par/rcmd_reply_data_6" BEL "u_sru_cmd_par/rcmd_reply_data_5" BEL "u_sru_cmd_par/rcmd_reply_data_4" BEL "u_sru_cmd_par/rcmd_reply_data_3" BEL "u_sru_cmd_par/rcmd_reply_data_2" BEL "u_sru_cmd_par/rcmd_reply_data_1" BEL "u_sru_cmd_par/rcmd_reply_data_0" BEL "u_sru_cmd_par/spill_d" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_1" BEL 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"u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_cmd_par/FastCmd_i" BEL "u_sru_cmd_par/test_pulse_en" BEL "htrig_d" BEL "spill_sync_d" BEL "sru_trig_synced_out_nim" BEL "u_sru_40dtc_top/DTCRamAllFlag_i" BEL "u_sru_cmd_par/reset_cmd" BEL "u_sru_trigger/tlu_event_number_15" BEL "u_sru_trigger/tlu_event_number_14" BEL "u_sru_trigger/tlu_event_number_13" BEL "u_sru_trigger/tlu_event_number_12" BEL "u_sru_trigger/tlu_event_number_11" BEL "u_sru_trigger/tlu_event_number_10" BEL "u_sru_trigger/tlu_event_number_9" BEL "u_sru_trigger/tlu_event_number_8" BEL "u_sru_trigger/tlu_event_number_7" BEL "u_sru_trigger/tlu_event_number_6" BEL "u_sru_trigger/tlu_event_number_5" BEL "u_sru_trigger/tlu_event_number_4" BEL "u_sru_trigger/tlu_event_number_3" BEL "u_sru_trigger/tlu_event_number_2" BEL "u_sru_trigger/tlu_event_number_1" BEL "u_sru_trigger/tlu_event_number_0" BEL "u_sru_trigger/tlu_event_number_shift_16" BEL "u_sru_trigger/tlu_event_number_shift_15" BEL "u_sru_trigger/tlu_event_number_shift_14" BEL "u_sru_trigger/tlu_event_number_shift_13" BEL "u_sru_trigger/tlu_event_number_shift_12" BEL "u_sru_trigger/tlu_event_number_shift_11" BEL "u_sru_trigger/tlu_event_number_shift_10" BEL "u_sru_trigger/tlu_event_number_shift_9" BEL "u_sru_trigger/tlu_event_number_shift_8" BEL "u_sru_trigger/tlu_event_number_shift_7" BEL "u_sru_trigger/tlu_event_number_shift_6" BEL "u_sru_trigger/tlu_event_number_shift_5" BEL "u_sru_trigger/tlu_event_number_shift_4" BEL "u_sru_trigger/tlu_event_number_shift_3" BEL "u_sru_trigger/tlu_event_number_shift_2" BEL "u_sru_trigger/tlu_event_number_shift_1" BEL "u_sru_trigger/tlu_event_number_shift_0" BEL "u_sru_trigger/u_ttc_decoder/st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/ttc_l1" BEL "u_sru_trigger/u_ttc_decoder/ttc_l0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_31" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_30" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_29" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_28" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_27" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_26" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_25" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_24" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_23" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_22" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_21" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_20" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_19" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_18" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_17" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_16" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_15" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_14" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_13" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_23" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_22" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_21" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_20" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_19" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_18" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_17" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_16" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_15" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_14" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_13" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/ttc_l2r" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/ttc_l2aMesRdy" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_59" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_58" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_57" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_56" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_55" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_54" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_53" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_52" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_51" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_50" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_49" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_48" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_47" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_46" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_45" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_44" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_43" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_42" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_41" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_40" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_39" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_38" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_37" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_36" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_35" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_34" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_33" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_32" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_31" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_30" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_29" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_28" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_27" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_26" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_25" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_24" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_23" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_22" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_21" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_20" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_19" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_18" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_17" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_16" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_15" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_14" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_13" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_12" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_11" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_10" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_9" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_8" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_7" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_6" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_5" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_4" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_3" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_2" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_1" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_0" BEL "u_sru_trigger/u_trig_cnt/event_cnt_29" BEL "u_sru_trigger/u_trig_cnt/event_cnt_28" BEL "u_sru_trigger/u_trig_cnt/event_cnt_27" BEL "u_sru_trigger/u_trig_cnt/event_cnt_26" BEL "u_sru_trigger/u_trig_cnt/event_cnt_25" BEL "u_sru_trigger/u_trig_cnt/event_cnt_24" BEL "u_sru_trigger/u_trig_cnt/event_cnt_23" BEL "u_sru_trigger/u_trig_cnt/event_cnt_22" BEL "u_sru_trigger/u_trig_cnt/event_cnt_21" BEL "u_sru_trigger/u_trig_cnt/event_cnt_20" BEL "u_sru_trigger/u_trig_cnt/event_cnt_19" BEL "u_sru_trigger/u_trig_cnt/event_cnt_18" BEL "u_sru_trigger/u_trig_cnt/event_cnt_17" BEL "u_sru_trigger/u_trig_cnt/event_cnt_16" BEL "u_sru_trigger/u_trig_cnt/event_cnt_15" BEL "u_sru_trigger/u_trig_cnt/event_cnt_14" BEL "u_sru_trigger/u_trig_cnt/event_cnt_13" BEL "u_sru_trigger/u_trig_cnt/event_cnt_12" BEL "u_sru_trigger/u_trig_cnt/event_cnt_11" BEL "u_sru_trigger/u_trig_cnt/event_cnt_10" BEL "u_sru_trigger/u_trig_cnt/event_cnt_9" BEL "u_sru_trigger/u_trig_cnt/event_cnt_8" BEL "u_sru_trigger/u_trig_cnt/event_cnt_7" BEL "u_sru_trigger/u_trig_cnt/event_cnt_6" BEL "u_sru_trigger/u_trig_cnt/event_cnt_5" BEL "u_sru_trigger/u_trig_cnt/event_cnt_4" BEL "u_sru_trigger/u_trig_cnt/event_cnt_3" BEL "u_sru_trigger/u_trig_cnt/event_cnt_2" BEL "u_sru_trigger/u_trig_cnt/event_cnt_1" BEL "u_sru_trigger/u_trig_cnt/event_cnt_0" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_31" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_30" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_29" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_28" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_27" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_26" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_25" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_24" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_23" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_22" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_21" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_20" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_19" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_18" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_17" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_16" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_15" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_14" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_13" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_12" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_11" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_10" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_9" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_8" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_7" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_6" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_5" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_4" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_3" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_2" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_1" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_0" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_31" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_30" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_29" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_28" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_27" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_26" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_25" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_24" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_23" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_22" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_21" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_20" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_19" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_18" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_17" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_16" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_15" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_14" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_13" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_12" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_11" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_10" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_9" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_8" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_7" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_6" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_5" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_4" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_3" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_2" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_1" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_0" BEL "u_sru_trigger/u_trig_cnt/event_countdown_31" BEL "u_sru_trigger/u_trig_cnt/event_countdown_30" BEL "u_sru_trigger/u_trig_cnt/event_countdown_29" BEL "u_sru_trigger/u_trig_cnt/event_countdown_28" BEL "u_sru_trigger/u_trig_cnt/event_countdown_27" BEL "u_sru_trigger/u_trig_cnt/event_countdown_26" BEL "u_sru_trigger/u_trig_cnt/event_countdown_25" BEL "u_sru_trigger/u_trig_cnt/event_countdown_24" BEL "u_sru_trigger/u_trig_cnt/event_countdown_23" BEL "u_sru_trigger/u_trig_cnt/event_countdown_22" BEL "u_sru_trigger/u_trig_cnt/event_countdown_21" BEL "u_sru_trigger/u_trig_cnt/event_countdown_20" BEL "u_sru_trigger/u_trig_cnt/event_countdown_19" BEL "u_sru_trigger/u_trig_cnt/event_countdown_18" BEL "u_sru_trigger/u_trig_cnt/event_countdown_17" BEL "u_sru_trigger/u_trig_cnt/event_countdown_16" BEL "u_sru_trigger/u_trig_cnt/event_countdown_15" BEL "u_sru_trigger/u_trig_cnt/event_countdown_14" BEL "u_sru_trigger/u_trig_cnt/event_countdown_13" BEL "u_sru_trigger/u_trig_cnt/event_countdown_12" BEL "u_sru_trigger/u_trig_cnt/event_countdown_11" BEL "u_sru_trigger/u_trig_cnt/event_countdown_10" BEL "u_sru_trigger/u_trig_cnt/event_countdown_9" BEL "u_sru_trigger/u_trig_cnt/event_countdown_8" BEL "u_sru_trigger/u_trig_cnt/event_countdown_7" BEL "u_sru_trigger/u_trig_cnt/event_countdown_6" BEL "u_sru_trigger/u_trig_cnt/event_countdown_5" BEL "u_sru_trigger/u_trig_cnt/event_countdown_4" BEL "u_sru_trigger/u_trig_cnt/event_countdown_3" BEL "u_sru_trigger/u_trig_cnt/event_countdown_2" BEL "u_sru_trigger/u_trig_cnt/event_countdown_1" BEL "u_sru_trigger/u_trig_cnt/event_countdown_0" BEL "u_sru_trigger/u_trig_cnt/clkcntb_3" BEL "u_sru_trigger/u_trig_cnt/clkcntb_2" BEL "u_sru_trigger/u_trig_cnt/clkcntb_1" BEL "u_sru_trigger/u_trig_cnt/clkcntb_0" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/timestamp_59" BEL "u_sru_trigger/u_trig_cnt/timestamp_58" BEL "u_sru_trigger/u_trig_cnt/timestamp_57" BEL "u_sru_trigger/u_trig_cnt/timestamp_56" BEL "u_sru_trigger/u_trig_cnt/timestamp_55" BEL "u_sru_trigger/u_trig_cnt/timestamp_54" BEL "u_sru_trigger/u_trig_cnt/timestamp_53" BEL "u_sru_trigger/u_trig_cnt/timestamp_52" BEL "u_sru_trigger/u_trig_cnt/timestamp_51" BEL "u_sru_trigger/u_trig_cnt/timestamp_50" BEL "u_sru_trigger/u_trig_cnt/timestamp_49" BEL "u_sru_trigger/u_trig_cnt/timestamp_48" BEL "u_sru_trigger/u_trig_cnt/timestamp_47" BEL "u_sru_trigger/u_trig_cnt/timestamp_46" BEL "u_sru_trigger/u_trig_cnt/timestamp_45" BEL "u_sru_trigger/u_trig_cnt/timestamp_44" BEL "u_sru_trigger/u_trig_cnt/timestamp_43" BEL "u_sru_trigger/u_trig_cnt/timestamp_42" BEL "u_sru_trigger/u_trig_cnt/timestamp_41" BEL "u_sru_trigger/u_trig_cnt/timestamp_40" BEL "u_sru_trigger/u_trig_cnt/timestamp_39" BEL "u_sru_trigger/u_trig_cnt/timestamp_38" BEL "u_sru_trigger/u_trig_cnt/timestamp_37" BEL "u_sru_trigger/u_trig_cnt/timestamp_36" BEL "u_sru_trigger/u_trig_cnt/timestamp_35" BEL "u_sru_trigger/u_trig_cnt/timestamp_34" BEL "u_sru_trigger/u_trig_cnt/timestamp_33" BEL "u_sru_trigger/u_trig_cnt/timestamp_32" BEL "u_sru_trigger/u_trig_cnt/timestamp_31" BEL "u_sru_trigger/u_trig_cnt/timestamp_30" BEL "u_sru_trigger/u_trig_cnt/timestamp_29" BEL "u_sru_trigger/u_trig_cnt/timestamp_28" BEL "u_sru_trigger/u_trig_cnt/timestamp_27" BEL "u_sru_trigger/u_trig_cnt/timestamp_26" BEL "u_sru_trigger/u_trig_cnt/timestamp_25" BEL "u_sru_trigger/u_trig_cnt/timestamp_24" BEL "u_sru_trigger/u_trig_cnt/timestamp_23" BEL "u_sru_trigger/u_trig_cnt/timestamp_22" BEL "u_sru_trigger/u_trig_cnt/timestamp_21" BEL "u_sru_trigger/u_trig_cnt/timestamp_20" BEL "u_sru_trigger/u_trig_cnt/timestamp_19" BEL "u_sru_trigger/u_trig_cnt/timestamp_18" BEL "u_sru_trigger/u_trig_cnt/timestamp_17" BEL "u_sru_trigger/u_trig_cnt/timestamp_16" BEL "u_sru_trigger/u_trig_cnt/timestamp_15" BEL "u_sru_trigger/u_trig_cnt/timestamp_14" BEL "u_sru_trigger/u_trig_cnt/timestamp_13" BEL "u_sru_trigger/u_trig_cnt/timestamp_12" BEL "u_sru_trigger/u_trig_cnt/timestamp_11" BEL "u_sru_trigger/u_trig_cnt/timestamp_10" BEL "u_sru_trigger/u_trig_cnt/timestamp_9" BEL "u_sru_trigger/u_trig_cnt/timestamp_8" BEL "u_sru_trigger/u_trig_cnt/timestamp_7" BEL "u_sru_trigger/u_trig_cnt/timestamp_6" BEL "u_sru_trigger/u_trig_cnt/timestamp_5" BEL "u_sru_trigger/u_trig_cnt/timestamp_4" BEL "u_sru_trigger/u_trig_cnt/timestamp_3" BEL "u_sru_trigger/u_trig_cnt/timestamp_2" BEL "u_sru_trigger/u_trig_cnt/timestamp_1" BEL "u_sru_trigger/u_trig_cnt/timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/abortcmd" BEL "u_sru_trigger/u_trig_cnt/rdocmd" BEL "u_sru_trigger/u_trig_cnt/event_cnt_wr_en" BEL "u_sru_trigger/u_trig_cnt/stc" BEL "u_sru_trigger/u_trig_cnt/stb" BEL "u_sru_trigger/u_trig_cnt/stall_events" BEL "u_sru_trigger/u_trig_cnt/BusyFlag_d" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd4" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_15" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_14" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_13" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_12" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_11" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_10" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_9" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_8" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_7" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_6" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_5" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_4" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_3" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_2" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_1" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_0" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd1" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd2" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd3" BEL "u_sru_trigger/u_test_trig_gen/sta_FSM_FFd1" BEL "u_sru_trigger/u_test_trig_gen/sta_FSM_FFd2" BEL "u_sru_trigger/u_test_trig_gen/test_trig" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_15" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_14" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_13" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_12" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_11" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_10" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_9" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_8" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_7" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_6" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_5" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_4" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_3" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_2" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_1" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_0" BEL "u_sru_trigger/u_test_trig_gen/test_l0" BEL "u_sru_trigger/u_test_trig_gen/test_l2a" BEL "u_sru_trigger/u_test_trig_gen/test_l1" BEL "u_sru_trigger/u_test_trig_gen/l0_trig" BEL "u_sru_trigger/u_test_trig_gen/test_pulse" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd3" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_11" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_10" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_9" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_8" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_7" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_6" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_5" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_4" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_3" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_2" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_1" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_0" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd1" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd4" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd2" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd6" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd7" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd5" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd8" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd9" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd10" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd11" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd13" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd14" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd12" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd16" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd17" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd15" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd18" BEL "u_sru_trigger/u_trig_err_detect/DtcRamClr" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_20" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_19" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_18" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_17" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_16" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_15" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_13" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_11" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_9" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_8" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_7" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_6" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_5" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_4" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_3" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_2" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_1" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_0" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_15" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_14" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_13" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_12" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_11" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_10" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_9" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_8" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_7" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_6" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_5" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_4" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_3" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_2" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_1" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_0" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_5" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_2" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_1" BEL "u_sru_trigger/u_trig_err_detect/abortcmd_c" BEL "u_sru_trigger/u_trig_err_detect/rdocmd_c" BEL "u_sru_trigger/u_trig_err_detect/trig_busy" BEL "u_sru_trigger/u_trig_err_detect/ddl_tx_start_i" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_cmd_par/synch_dcs/o" BEL "u_sru_cmd_par/synch_dcs/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_40/Mshreg_o" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/last_packet_sync_ff_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/Mshreg_last_packet_sync_ff_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_d" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_39" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_38" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_37" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_36" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_35" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_34" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_33" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_32" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_31" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_30" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_29" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_28" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_27" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_26" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_25" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_24" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_23" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_22" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_21" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_20" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_19" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_18" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_17" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_16" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_15" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_14" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_13" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_12" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_11" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_10" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_9" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_8" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/last_packet_sync_ff_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_0" BEL "u_main_clk_gen/TrigIOClkSel" BEL "u_SCLKPhaseDetect/cnt_i_1" BEL "u_SCLKPhaseDetect/cnt_i_0" BEL "u_SCLKPhaseDetect/st_FSM_FFd1" BEL "u_SCLKPhaseDetect/st_FSM_FFd2" BEL "u_SCLKPhaseDetect/sclkphasecnt_1" BEL "u_SCLKPhaseDetect/sclkphasecnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/fifo_rd_en" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_dv" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_15" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_14" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_13" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_12" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_11" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_10" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_9" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_8" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_7" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_6" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_5" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_4" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_3" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_2" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_1" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_0" BEL "u_sru_cmd_par/u_ResetSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_ResetSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_ResetSwitch/pulse_out_i" BEL "u_sru_cmd_par/u_BusyClrSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_BusyClrSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_BusyClrSwitch/pulse_out_i" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/pulse_out_i" BEL "u_sru_cmd_par/usrudcsreplyack/st_FSM_FFd1" BEL "u_sru_cmd_par/usrudcsreplyack/st_FSM_FFd2" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_update" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_63" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_62" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_61" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_60" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_59" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_58" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_57" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_56" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_55" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_54" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_53" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_52" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_51" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_50" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_49" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_48" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_47" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_46" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_45" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_44" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_43" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_42" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_41" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_40" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_39" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_38" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_37" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_36" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_35" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_34" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_33" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_32" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_31" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_30" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_29" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_28" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_27" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_26" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_25" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_24" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_23" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_22" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_21" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_20" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_19" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_18" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_17" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_16" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_15" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_14" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_13" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_12" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_11" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_10" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_9" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_8" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_7" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_6" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_5" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_4" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_3" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_2" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_1" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_0" PIN "u_sru_cmd_par/u_srutempmonitor/SYSMON_INST_pins<10>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<65>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout4_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout3_1 = BEL "htrig_number_d" BEL "spill_sync_dd" BEL "u_sru_40dtc_top/DtcRamFlag_ii_39" BEL "u_sru_40dtc_top/DtcRamFlag_ii_38" BEL "u_sru_40dtc_top/DtcRamFlag_ii_37" BEL "u_sru_40dtc_top/DtcRamFlag_ii_36" BEL "u_sru_40dtc_top/DtcRamFlag_ii_35" BEL "u_sru_40dtc_top/DtcRamFlag_ii_34" BEL "u_sru_40dtc_top/DtcRamFlag_ii_33" BEL "u_sru_40dtc_top/DtcRamFlag_ii_32" BEL "u_sru_40dtc_top/DtcRamFlag_ii_31" BEL "u_sru_40dtc_top/DtcRamFlag_ii_30" BEL "u_sru_40dtc_top/DtcRamFlag_ii_29" BEL "u_sru_40dtc_top/DtcRamFlag_ii_28" BEL "u_sru_40dtc_top/DtcRamFlag_ii_27" BEL "u_sru_40dtc_top/DtcRamFlag_ii_26" BEL "u_sru_40dtc_top/DtcRamFlag_ii_25" BEL "u_sru_40dtc_top/DtcRamFlag_ii_24" BEL "u_sru_40dtc_top/DtcRamFlag_ii_23" BEL "u_sru_40dtc_top/DtcRamFlag_ii_22" BEL "u_sru_40dtc_top/DtcRamFlag_ii_21" BEL "u_sru_40dtc_top/DtcRamFlag_ii_20" BEL "u_sru_40dtc_top/DtcRamFlag_ii_19" BEL "u_sru_40dtc_top/DtcRamFlag_ii_18" BEL "u_sru_40dtc_top/DtcRamFlag_ii_17" BEL "u_sru_40dtc_top/DtcRamFlag_ii_16" BEL "u_sru_40dtc_top/DtcRamFlag_ii_15" BEL "u_sru_40dtc_top/DtcRamFlag_ii_14" BEL "u_sru_40dtc_top/DtcRamFlag_ii_13" BEL "u_sru_40dtc_top/DtcRamFlag_ii_12" BEL "u_sru_40dtc_top/DtcRamFlag_ii_11" BEL "u_sru_40dtc_top/DtcRamFlag_ii_10" BEL "u_sru_40dtc_top/DtcRamFlag_ii_9" BEL "u_sru_40dtc_top/DtcRamFlag_ii_8" BEL "u_sru_40dtc_top/DtcRamFlag_ii_7" BEL "u_sru_40dtc_top/DtcRamFlag_ii_6" BEL "u_sru_40dtc_top/DtcRamFlag_ii_5" BEL "u_sru_40dtc_top/DtcRamFlag_ii_4" BEL "u_sru_40dtc_top/DtcRamFlag_ii_3" BEL "u_sru_40dtc_top/DtcRamFlag_ii_2" BEL "u_sru_40dtc_top/DtcRamFlag_ii_1" BEL "u_sru_40dtc_top/DtcRamFlag_ii_0" BEL "u_sru_40dtc_top/abortcmd_i_39" BEL "u_sru_40dtc_top/abortcmd_i_38" BEL "u_sru_40dtc_top/abortcmd_i_37" BEL "u_sru_40dtc_top/abortcmd_i_36" BEL "u_sru_40dtc_top/abortcmd_i_35" BEL "u_sru_40dtc_top/abortcmd_i_34" BEL "u_sru_40dtc_top/abortcmd_i_33" BEL "u_sru_40dtc_top/abortcmd_i_32" BEL "u_sru_40dtc_top/abortcmd_i_31" BEL "u_sru_40dtc_top/abortcmd_i_30" BEL "u_sru_40dtc_top/abortcmd_i_29" BEL "u_sru_40dtc_top/abortcmd_i_28" BEL "u_sru_40dtc_top/abortcmd_i_27" BEL "u_sru_40dtc_top/abortcmd_i_26" BEL "u_sru_40dtc_top/abortcmd_i_25" BEL "u_sru_40dtc_top/abortcmd_i_24" BEL "u_sru_40dtc_top/abortcmd_i_23" BEL "u_sru_40dtc_top/abortcmd_i_22" BEL "u_sru_40dtc_top/abortcmd_i_21" BEL "u_sru_40dtc_top/abortcmd_i_20" BEL "u_sru_40dtc_top/abortcmd_i_19" BEL "u_sru_40dtc_top/abortcmd_i_18" BEL "u_sru_40dtc_top/abortcmd_i_17" BEL "u_sru_40dtc_top/abortcmd_i_16" BEL "u_sru_40dtc_top/abortcmd_i_15" BEL "u_sru_40dtc_top/abortcmd_i_14" BEL "u_sru_40dtc_top/abortcmd_i_13" BEL "u_sru_40dtc_top/abortcmd_i_12" BEL "u_sru_40dtc_top/abortcmd_i_11" BEL "u_sru_40dtc_top/abortcmd_i_10" BEL "u_sru_40dtc_top/abortcmd_i_9" BEL "u_sru_40dtc_top/abortcmd_i_8" BEL "u_sru_40dtc_top/abortcmd_i_7" BEL "u_sru_40dtc_top/abortcmd_i_6" BEL "u_sru_40dtc_top/abortcmd_i_5" BEL "u_sru_40dtc_top/abortcmd_i_4" BEL "u_sru_40dtc_top/abortcmd_i_3" BEL "u_sru_40dtc_top/abortcmd_i_2" BEL "u_sru_40dtc_top/abortcmd_i_1" BEL "u_sru_40dtc_top/abortcmd_i_0" BEL "u_sru_40dtc_top/DTCEventRdy_i_39" BEL "u_sru_40dtc_top/DTCEventRdy_i_38" BEL "u_sru_40dtc_top/DTCEventRdy_i_37" BEL "u_sru_40dtc_top/DTCEventRdy_i_36" BEL "u_sru_40dtc_top/DTCEventRdy_i_35" BEL "u_sru_40dtc_top/DTCEventRdy_i_34" BEL "u_sru_40dtc_top/DTCEventRdy_i_33" BEL "u_sru_40dtc_top/DTCEventRdy_i_32" BEL "u_sru_40dtc_top/DTCEventRdy_i_31" BEL "u_sru_40dtc_top/DTCEventRdy_i_30" BEL "u_sru_40dtc_top/DTCEventRdy_i_29" BEL "u_sru_40dtc_top/DTCEventRdy_i_28" BEL "u_sru_40dtc_top/DTCEventRdy_i_27" BEL "u_sru_40dtc_top/DTCEventRdy_i_26" BEL "u_sru_40dtc_top/DTCEventRdy_i_25" BEL "u_sru_40dtc_top/DTCEventRdy_i_24" BEL "u_sru_40dtc_top/DTCEventRdy_i_23" BEL "u_sru_40dtc_top/DTCEventRdy_i_22" BEL "u_sru_40dtc_top/DTCEventRdy_i_21" BEL "u_sru_40dtc_top/DTCEventRdy_i_20" BEL "u_sru_40dtc_top/DTCEventRdy_i_19" BEL "u_sru_40dtc_top/DTCEventRdy_i_18" BEL "u_sru_40dtc_top/DTCEventRdy_i_17" BEL "u_sru_40dtc_top/DTCEventRdy_i_16" BEL "u_sru_40dtc_top/DTCEventRdy_i_15" BEL "u_sru_40dtc_top/DTCEventRdy_i_14" BEL "u_sru_40dtc_top/DTCEventRdy_i_13" BEL "u_sru_40dtc_top/DTCEventRdy_i_12" BEL "u_sru_40dtc_top/DTCEventRdy_i_11" BEL "u_sru_40dtc_top/DTCEventRdy_i_10" BEL "u_sru_40dtc_top/DTCEventRdy_i_9" BEL "u_sru_40dtc_top/DTCEventRdy_i_8" BEL "u_sru_40dtc_top/DTCEventRdy_i_7" BEL "u_sru_40dtc_top/DTCEventRdy_i_6" BEL "u_sru_40dtc_top/DTCEventRdy_i_5" BEL "u_sru_40dtc_top/DTCEventRdy_i_4" BEL "u_sru_40dtc_top/DTCEventRdy_i_3" BEL "u_sru_40dtc_top/DTCEventRdy_i_2" BEL "u_sru_40dtc_top/DTCEventRdy_i_1" BEL "u_sru_40dtc_top/DTCEventRdy_i_0" BEL "u_sru_40dtc_top/FeeTrig_i_39" BEL "u_sru_40dtc_top/FeeTrig_i_38" BEL "u_sru_40dtc_top/FeeTrig_i_37" BEL "u_sru_40dtc_top/FeeTrig_i_36" BEL "u_sru_40dtc_top/FeeTrig_i_35" BEL "u_sru_40dtc_top/FeeTrig_i_34" BEL "u_sru_40dtc_top/FeeTrig_i_33" BEL "u_sru_40dtc_top/FeeTrig_i_32" BEL "u_sru_40dtc_top/FeeTrig_i_31" BEL "u_sru_40dtc_top/FeeTrig_i_30" BEL "u_sru_40dtc_top/FeeTrig_i_29" BEL "u_sru_40dtc_top/FeeTrig_i_28" BEL "u_sru_40dtc_top/FeeTrig_i_27" BEL "u_sru_40dtc_top/FeeTrig_i_26" BEL "u_sru_40dtc_top/FeeTrig_i_25" BEL "u_sru_40dtc_top/FeeTrig_i_24" BEL "u_sru_40dtc_top/FeeTrig_i_23" BEL "u_sru_40dtc_top/FeeTrig_i_22" BEL "u_sru_40dtc_top/FeeTrig_i_21" BEL "u_sru_40dtc_top/FeeTrig_i_20" BEL "u_sru_40dtc_top/FeeTrig_i_19" BEL "u_sru_40dtc_top/FeeTrig_i_18" BEL "u_sru_40dtc_top/FeeTrig_i_17" BEL "u_sru_40dtc_top/FeeTrig_i_16" BEL "u_sru_40dtc_top/FeeTrig_i_15" BEL "u_sru_40dtc_top/FeeTrig_i_14" BEL "u_sru_40dtc_top/FeeTrig_i_13" BEL "u_sru_40dtc_top/FeeTrig_i_12" BEL "u_sru_40dtc_top/FeeTrig_i_11" BEL "u_sru_40dtc_top/FeeTrig_i_10" BEL "u_sru_40dtc_top/FeeTrig_i_9" BEL "u_sru_40dtc_top/FeeTrig_i_8" BEL "u_sru_40dtc_top/FeeTrig_i_7" BEL "u_sru_40dtc_top/FeeTrig_i_6" BEL "u_sru_40dtc_top/FeeTrig_i_5" BEL "u_sru_40dtc_top/FeeTrig_i_4" BEL "u_sru_40dtc_top/FeeTrig_i_3" BEL "u_sru_40dtc_top/FeeTrig_i_2" BEL "u_sru_40dtc_top/FeeTrig_i_1" BEL "u_sru_40dtc_top/FeeTrig_i_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/clk_ODELAY" BEL "u_sru_cmd_par/BusyCnt_31" BEL "u_sru_cmd_par/BusyCnt_30" BEL "u_sru_cmd_par/BusyCnt_29" BEL "u_sru_cmd_par/BusyCnt_28" BEL "u_sru_cmd_par/BusyCnt_27" BEL "u_sru_cmd_par/BusyCnt_26" BEL "u_sru_cmd_par/BusyCnt_25" BEL "u_sru_cmd_par/BusyCnt_24" BEL "u_sru_cmd_par/BusyCnt_23" BEL "u_sru_cmd_par/BusyCnt_22" BEL "u_sru_cmd_par/BusyCnt_21" BEL "u_sru_cmd_par/BusyCnt_20" BEL "u_sru_cmd_par/BusyCnt_19" BEL "u_sru_cmd_par/BusyCnt_18" BEL "u_sru_cmd_par/BusyCnt_17" BEL "u_sru_cmd_par/BusyCnt_16" BEL "u_sru_cmd_par/BusyCnt_15" BEL "u_sru_cmd_par/BusyCnt_14" BEL "u_sru_cmd_par/BusyCnt_13" BEL "u_sru_cmd_par/BusyCnt_12" BEL "u_sru_cmd_par/BusyCnt_11" BEL "u_sru_cmd_par/BusyCnt_10" BEL "u_sru_cmd_par/BusyCnt_9" BEL "u_sru_cmd_par/BusyCnt_8" BEL "u_sru_cmd_par/BusyCnt_7" BEL "u_sru_cmd_par/BusyCnt_6" BEL "u_sru_cmd_par/BusyCnt_5" BEL "u_sru_cmd_par/BusyCnt_4" BEL "u_sru_cmd_par/BusyCnt_3" BEL "u_sru_cmd_par/BusyCnt_2" BEL "u_sru_cmd_par/BusyCnt_1" BEL "u_sru_cmd_par/BusyCnt_0" BEL "u_sru_cmd_par/SRUMonData_15" BEL "u_sru_cmd_par/SRUMonData_14" BEL "u_sru_cmd_par/SRUMonData_13" BEL "u_sru_cmd_par/SRUMonData_12" BEL "u_sru_cmd_par/SRUMonData_11" BEL "u_sru_cmd_par/SRUMonData_10" BEL "u_sru_cmd_par/SRUMonData_9" BEL "u_sru_cmd_par/SRUMonData_8" BEL "u_sru_cmd_par/SRUMonData_7" BEL "u_sru_cmd_par/SRUMonData_6" BEL "u_sru_cmd_par/SRUMonData_5" BEL "u_sru_cmd_par/SRUMonData_4" BEL "u_sru_cmd_par/SRUMonData_3" BEL "u_sru_cmd_par/SRUMonData_2" BEL "u_sru_cmd_par/SRUMonData_1" BEL "u_sru_cmd_par/SRUMonData_0" BEL "u_sru_cmd_par/FastCmdCode_7" BEL "u_sru_cmd_par/FastCmdCode_6" BEL "u_sru_cmd_par/FastCmdCode_5" BEL "u_sru_cmd_par/FastCmdCode_4" BEL "u_sru_cmd_par/FastCmdCode_3" BEL "u_sru_cmd_par/FastCmdCode_2" BEL "u_sru_cmd_par/FastCmdCode_1" BEL "u_sru_cmd_par/FastCmdCode_0" BEL "u_sru_cmd_par/walign_reg_31" BEL "u_sru_cmd_par/walign_reg_30" BEL "u_sru_cmd_par/walign_reg_29" BEL "u_sru_cmd_par/walign_reg_28" BEL "u_sru_cmd_par/walign_reg_27" BEL "u_sru_cmd_par/walign_reg_26" BEL "u_sru_cmd_par/walign_reg_25" BEL "u_sru_cmd_par/walign_reg_24" BEL "u_sru_cmd_par/walign_reg_23" BEL "u_sru_cmd_par/walign_reg_22" BEL "u_sru_cmd_par/walign_reg_21" BEL "u_sru_cmd_par/walign_reg_20" BEL "u_sru_cmd_par/walign_reg_19" BEL "u_sru_cmd_par/walign_reg_18" BEL "u_sru_cmd_par/walign_reg_17" BEL "u_sru_cmd_par/walign_reg_16" BEL "u_sru_cmd_par/walign_reg_15" BEL "u_sru_cmd_par/walign_reg_14" BEL "u_sru_cmd_par/walign_reg_13" BEL "u_sru_cmd_par/walign_reg_12" BEL "u_sru_cmd_par/walign_reg_11" BEL "u_sru_cmd_par/walign_reg_10" BEL "u_sru_cmd_par/walign_reg_9" BEL "u_sru_cmd_par/walign_reg_8" BEL "u_sru_cmd_par/walign_reg_7" BEL "u_sru_cmd_par/walign_reg_6" BEL "u_sru_cmd_par/walign_reg_5" BEL "u_sru_cmd_par/walign_reg_4" BEL "u_sru_cmd_par/walign_reg_3" BEL "u_sru_cmd_par/walign_reg_2" BEL "u_sru_cmd_par/walign_reg_1" BEL "u_sru_cmd_par/walign_reg_0" BEL "u_sru_cmd_par/errtest_reg_31" BEL "u_sru_cmd_par/errtest_reg_30" BEL "u_sru_cmd_par/errtest_reg_29" BEL "u_sru_cmd_par/errtest_reg_28" BEL "u_sru_cmd_par/errtest_reg_27" BEL "u_sru_cmd_par/errtest_reg_26" BEL "u_sru_cmd_par/errtest_reg_25" BEL "u_sru_cmd_par/errtest_reg_24" BEL "u_sru_cmd_par/errtest_reg_23" BEL "u_sru_cmd_par/errtest_reg_22" BEL "u_sru_cmd_par/errtest_reg_21" BEL "u_sru_cmd_par/errtest_reg_20" BEL "u_sru_cmd_par/errtest_reg_19" BEL "u_sru_cmd_par/errtest_reg_18" BEL "u_sru_cmd_par/errtest_reg_17" BEL "u_sru_cmd_par/errtest_reg_16" BEL "u_sru_cmd_par/errtest_reg_15" BEL "u_sru_cmd_par/errtest_reg_14" BEL "u_sru_cmd_par/errtest_reg_13" BEL "u_sru_cmd_par/errtest_reg_12" BEL "u_sru_cmd_par/errtest_reg_11" BEL "u_sru_cmd_par/errtest_reg_10" BEL "u_sru_cmd_par/errtest_reg_9" BEL "u_sru_cmd_par/errtest_reg_8" BEL "u_sru_cmd_par/errtest_reg_7" BEL "u_sru_cmd_par/errtest_reg_6" BEL "u_sru_cmd_par/errtest_reg_5" BEL "u_sru_cmd_par/errtest_reg_4" BEL "u_sru_cmd_par/errtest_reg_3" BEL "u_sru_cmd_par/errtest_reg_2" BEL "u_sru_cmd_par/errtest_reg_1" BEL "u_sru_cmd_par/errtest_reg_0" BEL "u_sru_cmd_par/FastCmd_reg_15" BEL "u_sru_cmd_par/FastCmd_reg_14" BEL "u_sru_cmd_par/FastCmd_reg_13" BEL "u_sru_cmd_par/FastCmd_reg_12" BEL "u_sru_cmd_par/FastCmd_reg_11" BEL "u_sru_cmd_par/FastCmd_reg_10" BEL "u_sru_cmd_par/FastCmd_reg_9" BEL "u_sru_cmd_par/FastCmd_reg_8" BEL "u_sru_cmd_par/FastCmd_reg_7" BEL "u_sru_cmd_par/FastCmd_reg_6" BEL "u_sru_cmd_par/FastCmd_reg_5" BEL "u_sru_cmd_par/FastCmd_reg_4" BEL "u_sru_cmd_par/FastCmd_reg_3" BEL "u_sru_cmd_par/FastCmd_reg_2" BEL "u_sru_cmd_par/FastCmd_reg_1" BEL "u_sru_cmd_par/FastCmd_reg_0" BEL "u_sru_cmd_par/dtc_out_phase_cmd" BEL "u_sru_cmd_par/event_countdown_wr_en" BEL "u_sru_cmd_par/timestamp_clr" BEL "u_sru_cmd_par/busyclr_cmd" BEL "u_sru_cmd_par/trigerr_clr" BEL "u_sru_cmd_par/trigcnt_clr" BEL "u_sru_cmd_par/evnt_clr" BEL "u_sru_cmd_par/pscmd" BEL "u_sru_cmd_par/strig_cmd" BEL "u_sru_cmd_par/FPGAReload_i" BEL "u_sru_cmd_par/errtest_cmd" BEL "u_sru_cmd_par/walign_cmd" BEL "u_sru_cmd_par/test_pulse_width_9" BEL "u_sru_cmd_par/test_pulse_width_8" BEL "u_sru_cmd_par/test_pulse_width_7" BEL "u_sru_cmd_par/test_pulse_width_6" BEL "u_sru_cmd_par/test_pulse_width_5" BEL "u_sru_cmd_par/test_pulse_width_4" BEL "u_sru_cmd_par/test_pulse_width_3" BEL "u_sru_cmd_par/test_pulse_width_2" BEL "u_sru_cmd_par/test_pulse_width_1" BEL "u_sru_cmd_par/test_pulse_width_0" BEL "u_sru_cmd_par/testtrigcfg1_31" BEL "u_sru_cmd_par/testtrigcfg1_30" BEL "u_sru_cmd_par/testtrigcfg1_29" BEL "u_sru_cmd_par/testtrigcfg1_28" BEL "u_sru_cmd_par/testtrigcfg1_27" BEL "u_sru_cmd_par/testtrigcfg1_26" BEL "u_sru_cmd_par/testtrigcfg1_25" BEL "u_sru_cmd_par/testtrigcfg1_24" BEL "u_sru_cmd_par/testtrigcfg1_23" BEL "u_sru_cmd_par/testtrigcfg1_22" BEL "u_sru_cmd_par/testtrigcfg1_21" BEL "u_sru_cmd_par/testtrigcfg1_20" BEL "u_sru_cmd_par/testtrigcfg1_19" BEL "u_sru_cmd_par/testtrigcfg1_18" BEL "u_sru_cmd_par/testtrigcfg1_17" BEL "u_sru_cmd_par/testtrigcfg1_16" BEL "u_sru_cmd_par/testtrigcfg1_15" BEL "u_sru_cmd_par/testtrigcfg1_14" BEL "u_sru_cmd_par/testtrigcfg1_13" BEL "u_sru_cmd_par/testtrigcfg1_12" BEL "u_sru_cmd_par/testtrigcfg1_11" BEL "u_sru_cmd_par/testtrigcfg1_10" BEL "u_sru_cmd_par/testtrigcfg1_9" BEL "u_sru_cmd_par/testtrigcfg1_8" BEL "u_sru_cmd_par/testtrigcfg1_7" BEL "u_sru_cmd_par/testtrigcfg1_6" BEL "u_sru_cmd_par/testtrigcfg1_5" BEL "u_sru_cmd_par/testtrigcfg1_4" BEL "u_sru_cmd_par/testtrigcfg1_3" BEL "u_sru_cmd_par/testtrigcfg1_2" BEL "u_sru_cmd_par/testtrigcfg1_1" BEL "u_sru_cmd_par/testtrigcfg1_0" BEL "u_sru_cmd_par/test_pulse_start_15" BEL "u_sru_cmd_par/test_pulse_start_14" BEL "u_sru_cmd_par/test_pulse_start_13" BEL "u_sru_cmd_par/test_pulse_start_12" BEL "u_sru_cmd_par/test_pulse_start_11" BEL "u_sru_cmd_par/test_pulse_start_10" BEL "u_sru_cmd_par/test_pulse_start_9" BEL "u_sru_cmd_par/test_pulse_start_8" BEL "u_sru_cmd_par/test_pulse_start_7" BEL "u_sru_cmd_par/test_pulse_start_6" BEL "u_sru_cmd_par/test_pulse_start_5" BEL "u_sru_cmd_par/test_pulse_start_4" BEL "u_sru_cmd_par/test_pulse_start_3" BEL "u_sru_cmd_par/test_pulse_start_2" BEL "u_sru_cmd_par/test_pulse_start_1" BEL "u_sru_cmd_par/test_pulse_start_0" BEL "u_sru_cmd_par/ptrigcfg_16" BEL "u_sru_cmd_par/ptrigcfg_15" BEL "u_sru_cmd_par/ptrigcfg_14" BEL "u_sru_cmd_par/ptrigcfg_13" BEL "u_sru_cmd_par/ptrigcfg_12" BEL "u_sru_cmd_par/ptrigcfg_11" BEL "u_sru_cmd_par/ptrigcfg_10" BEL "u_sru_cmd_par/ptrigcfg_9" BEL "u_sru_cmd_par/ptrigcfg_8" BEL "u_sru_cmd_par/ptrigcfg_7" BEL "u_sru_cmd_par/ptrigcfg_6" BEL "u_sru_cmd_par/ptrigcfg_5" BEL "u_sru_cmd_par/ptrigcfg_4" BEL "u_sru_cmd_par/ptrigcfg_3" BEL "u_sru_cmd_par/ptrigcfg_2" BEL "u_sru_cmd_par/ptrigcfg_1" BEL "u_sru_cmd_par/ptrigcfg_0" BEL "u_sru_cmd_par/trigl2tw_31" BEL "u_sru_cmd_par/trigl2tw_30" BEL "u_sru_cmd_par/trigl2tw_29" BEL "u_sru_cmd_par/trigl2tw_28" BEL "u_sru_cmd_par/trigl2tw_27" BEL "u_sru_cmd_par/trigl2tw_26" BEL "u_sru_cmd_par/trigl2tw_25" BEL "u_sru_cmd_par/trigl2tw_24" BEL "u_sru_cmd_par/trigl2tw_23" BEL "u_sru_cmd_par/trigl2tw_22" BEL "u_sru_cmd_par/trigl2tw_21" BEL "u_sru_cmd_par/trigl2tw_20" BEL "u_sru_cmd_par/trigl2tw_19" BEL "u_sru_cmd_par/trigl2tw_18" BEL "u_sru_cmd_par/trigl2tw_17" BEL "u_sru_cmd_par/trigl2tw_16" BEL "u_sru_cmd_par/trigl2tw_15" BEL "u_sru_cmd_par/trigl2tw_14" BEL "u_sru_cmd_par/trigl2tw_13" BEL "u_sru_cmd_par/trigl2tw_12" BEL "u_sru_cmd_par/trigl2tw_11" BEL "u_sru_cmd_par/trigl2tw_10" BEL "u_sru_cmd_par/trigl2tw_9" BEL "u_sru_cmd_par/trigl2tw_8" BEL "u_sru_cmd_par/trigl2tw_7" BEL "u_sru_cmd_par/trigl2tw_6" BEL "u_sru_cmd_par/trigl2tw_5" BEL "u_sru_cmd_par/trigl2tw_4" BEL "u_sru_cmd_par/trigl2tw_3" BEL "u_sru_cmd_par/trigl2tw_2" BEL "u_sru_cmd_par/trigl2tw_1" BEL "u_sru_cmd_par/trigl2tw_0" BEL "u_sru_cmd_par/testtrigcfg0_31" BEL "u_sru_cmd_par/testtrigcfg0_30" BEL "u_sru_cmd_par/testtrigcfg0_29" BEL "u_sru_cmd_par/testtrigcfg0_28" BEL "u_sru_cmd_par/testtrigcfg0_27" BEL "u_sru_cmd_par/testtrigcfg0_26" BEL "u_sru_cmd_par/testtrigcfg0_25" BEL "u_sru_cmd_par/testtrigcfg0_24" BEL "u_sru_cmd_par/testtrigcfg0_23" BEL "u_sru_cmd_par/testtrigcfg0_22" BEL "u_sru_cmd_par/testtrigcfg0_21" BEL "u_sru_cmd_par/testtrigcfg0_20" BEL "u_sru_cmd_par/testtrigcfg0_19" BEL "u_sru_cmd_par/testtrigcfg0_18" BEL "u_sru_cmd_par/testtrigcfg0_17" BEL "u_sru_cmd_par/testtrigcfg0_16" BEL "u_sru_cmd_par/testtrigcfg0_15" BEL "u_sru_cmd_par/testtrigcfg0_14" BEL "u_sru_cmd_par/testtrigcfg0_13" BEL "u_sru_cmd_par/testtrigcfg0_12" BEL "u_sru_cmd_par/testtrigcfg0_11" BEL "u_sru_cmd_par/testtrigcfg0_10" BEL "u_sru_cmd_par/testtrigcfg0_9" BEL "u_sru_cmd_par/testtrigcfg0_8" BEL "u_sru_cmd_par/testtrigcfg0_7" BEL "u_sru_cmd_par/testtrigcfg0_6" BEL "u_sru_cmd_par/testtrigcfg0_5" BEL "u_sru_cmd_par/testtrigcfg0_4" BEL "u_sru_cmd_par/testtrigcfg0_3" BEL "u_sru_cmd_par/testtrigcfg0_2" BEL "u_sru_cmd_par/testtrigcfg0_1" BEL "u_sru_cmd_par/testtrigcfg0_0" BEL "u_sru_cmd_par/trigl1tw_31" BEL "u_sru_cmd_par/trigl1tw_30" BEL "u_sru_cmd_par/trigl1tw_29" BEL "u_sru_cmd_par/trigl1tw_28" BEL "u_sru_cmd_par/trigl1tw_27" BEL "u_sru_cmd_par/trigl1tw_26" BEL "u_sru_cmd_par/trigl1tw_25" BEL "u_sru_cmd_par/trigl1tw_24" BEL "u_sru_cmd_par/trigl1tw_23" BEL "u_sru_cmd_par/trigl1tw_22" BEL "u_sru_cmd_par/trigl1tw_21" BEL "u_sru_cmd_par/trigl1tw_20" BEL "u_sru_cmd_par/trigl1tw_19" BEL "u_sru_cmd_par/trigl1tw_18" BEL "u_sru_cmd_par/trigl1tw_17" BEL "u_sru_cmd_par/trigl1tw_16" BEL "u_sru_cmd_par/trigl1tw_15" BEL "u_sru_cmd_par/trigl1tw_14" BEL "u_sru_cmd_par/trigl1tw_13" BEL "u_sru_cmd_par/trigl1tw_12" BEL "u_sru_cmd_par/trigl1tw_11" BEL "u_sru_cmd_par/trigl1tw_10" BEL "u_sru_cmd_par/trigl1tw_9" BEL "u_sru_cmd_par/trigl1tw_8" BEL "u_sru_cmd_par/trigl1tw_7" BEL "u_sru_cmd_par/trigl1tw_6" BEL "u_sru_cmd_par/trigl1tw_5" BEL "u_sru_cmd_par/trigl1tw_4" BEL "u_sru_cmd_par/trigl1tw_3" BEL "u_sru_cmd_par/trigl1tw_2" BEL "u_sru_cmd_par/trigl1tw_1" BEL "u_sru_cmd_par/trigl1tw_0" BEL "u_sru_cmd_par/psscancfg_16" BEL "u_sru_cmd_par/psscancfg_15" BEL "u_sru_cmd_par/psscancfg_14" BEL "u_sru_cmd_par/psscancfg_13" BEL "u_sru_cmd_par/psscancfg_12" BEL "u_sru_cmd_par/psscancfg_11" BEL "u_sru_cmd_par/psscancfg_10" BEL "u_sru_cmd_par/psscancfg_9" BEL "u_sru_cmd_par/psscancfg_8" BEL "u_sru_cmd_par/psscancfg_7" BEL "u_sru_cmd_par/psscancfg_6" BEL "u_sru_cmd_par/psscancfg_5" BEL "u_sru_cmd_par/psscancfg_4" BEL "u_sru_cmd_par/psscancfg_3" BEL "u_sru_cmd_par/psscancfg_2" BEL "u_sru_cmd_par/psscancfg_1" BEL "u_sru_cmd_par/psscancfg_0" BEL "u_sru_cmd_par/dtc_power_en_39" BEL "u_sru_cmd_par/dtc_power_en_38" BEL "u_sru_cmd_par/dtc_power_en_37" BEL "u_sru_cmd_par/dtc_power_en_36" BEL "u_sru_cmd_par/dtc_power_en_35" BEL "u_sru_cmd_par/dtc_power_en_34" BEL "u_sru_cmd_par/dtc_power_en_33" BEL "u_sru_cmd_par/dtc_power_en_32" BEL "u_sru_cmd_par/dtc_power_en_31" BEL "u_sru_cmd_par/dtc_power_en_30" BEL "u_sru_cmd_par/dtc_power_en_29" BEL "u_sru_cmd_par/dtc_power_en_28" BEL "u_sru_cmd_par/dtc_power_en_27" BEL "u_sru_cmd_par/dtc_power_en_26" BEL "u_sru_cmd_par/dtc_power_en_25" BEL "u_sru_cmd_par/dtc_power_en_24" BEL "u_sru_cmd_par/dtc_power_en_23" BEL "u_sru_cmd_par/dtc_power_en_22" BEL "u_sru_cmd_par/dtc_power_en_21" BEL "u_sru_cmd_par/dtc_power_en_20" BEL "u_sru_cmd_par/dtc_power_en_19" BEL "u_sru_cmd_par/dtc_power_en_18" BEL "u_sru_cmd_par/dtc_power_en_17" BEL "u_sru_cmd_par/dtc_power_en_16" BEL "u_sru_cmd_par/dtc_power_en_15" BEL "u_sru_cmd_par/dtc_power_en_14" BEL "u_sru_cmd_par/dtc_power_en_13" BEL "u_sru_cmd_par/dtc_power_en_12" BEL "u_sru_cmd_par/dtc_power_en_11" BEL "u_sru_cmd_par/dtc_power_en_10" BEL "u_sru_cmd_par/dtc_power_en_9" BEL "u_sru_cmd_par/dtc_power_en_8" BEL "u_sru_cmd_par/dtc_power_en_7" BEL "u_sru_cmd_par/dtc_power_en_6" BEL "u_sru_cmd_par/dtc_power_en_5" BEL "u_sru_cmd_par/dtc_power_en_4" BEL "u_sru_cmd_par/dtc_power_en_3" BEL "u_sru_cmd_par/dtc_power_en_2" BEL "u_sru_cmd_par/dtc_power_en_1" BEL "u_sru_cmd_par/dtc_power_en_0" BEL "u_sru_cmd_par/dtc_out_phase_delay_4" BEL "u_sru_cmd_par/dtc_out_phase_delay_3" BEL "u_sru_cmd_par/dtc_out_phase_delay_2" BEL "u_sru_cmd_par/dtc_out_phase_delay_1" BEL "u_sru_cmd_par/dtc_out_phase_delay_0" BEL "u_sru_cmd_par/dtc_out_phase_channel_5" BEL "u_sru_cmd_par/dtc_out_phase_channel_4" BEL "u_sru_cmd_par/dtc_out_phase_channel_3" BEL "u_sru_cmd_par/dtc_out_phase_channel_2" BEL "u_sru_cmd_par/dtc_out_phase_channel_1" BEL "u_sru_cmd_par/dtc_out_phase_channel_0" BEL "u_sru_cmd_par/event_countdown_input_31" BEL "u_sru_cmd_par/event_countdown_input_30" BEL "u_sru_cmd_par/event_countdown_input_29" BEL "u_sru_cmd_par/event_countdown_input_28" BEL "u_sru_cmd_par/event_countdown_input_27" BEL "u_sru_cmd_par/event_countdown_input_26" BEL "u_sru_cmd_par/event_countdown_input_25" BEL "u_sru_cmd_par/event_countdown_input_24" BEL "u_sru_cmd_par/event_countdown_input_23" BEL "u_sru_cmd_par/event_countdown_input_22" BEL "u_sru_cmd_par/event_countdown_input_21" BEL "u_sru_cmd_par/event_countdown_input_20" BEL "u_sru_cmd_par/event_countdown_input_19" BEL "u_sru_cmd_par/event_countdown_input_18" BEL "u_sru_cmd_par/event_countdown_input_17" BEL "u_sru_cmd_par/event_countdown_input_16" BEL "u_sru_cmd_par/event_countdown_input_15" BEL "u_sru_cmd_par/event_countdown_input_14" BEL "u_sru_cmd_par/event_countdown_input_13" BEL "u_sru_cmd_par/event_countdown_input_12" BEL "u_sru_cmd_par/event_countdown_input_11" BEL "u_sru_cmd_par/event_countdown_input_10" BEL "u_sru_cmd_par/event_countdown_input_9" BEL "u_sru_cmd_par/event_countdown_input_8" BEL "u_sru_cmd_par/event_countdown_input_7" BEL "u_sru_cmd_par/event_countdown_input_6" BEL "u_sru_cmd_par/event_countdown_input_5" BEL "u_sru_cmd_par/event_countdown_input_4" BEL "u_sru_cmd_par/event_countdown_input_3" BEL "u_sru_cmd_par/event_countdown_input_2" BEL "u_sru_cmd_par/event_countdown_input_1" BEL "u_sru_cmd_par/event_countdown_input_0" BEL "u_sru_cmd_par/dtc_mon_sel_5" BEL "u_sru_cmd_par/dtc_mon_sel_4" BEL "u_sru_cmd_par/dtc_mon_sel_3" BEL "u_sru_cmd_par/dtc_mon_sel_2" BEL "u_sru_cmd_par/dtc_mon_sel_1" BEL "u_sru_cmd_par/dtc_mon_sel_0" BEL "u_sru_cmd_par/readout_ip_31" BEL "u_sru_cmd_par/readout_ip_30" BEL "u_sru_cmd_par/readout_ip_29" BEL "u_sru_cmd_par/readout_ip_28" BEL "u_sru_cmd_par/readout_ip_27" BEL "u_sru_cmd_par/readout_ip_26" BEL "u_sru_cmd_par/readout_ip_25" BEL "u_sru_cmd_par/readout_ip_24" BEL "u_sru_cmd_par/readout_ip_23" BEL "u_sru_cmd_par/readout_ip_22" BEL "u_sru_cmd_par/readout_ip_21" BEL "u_sru_cmd_par/readout_ip_20" BEL "u_sru_cmd_par/readout_ip_19" BEL "u_sru_cmd_par/readout_ip_18" BEL "u_sru_cmd_par/readout_ip_17" BEL "u_sru_cmd_par/readout_ip_16" BEL "u_sru_cmd_par/readout_ip_15" BEL "u_sru_cmd_par/readout_ip_14" BEL "u_sru_cmd_par/readout_ip_13" BEL "u_sru_cmd_par/readout_ip_12" BEL "u_sru_cmd_par/readout_ip_11" BEL "u_sru_cmd_par/readout_ip_10" BEL "u_sru_cmd_par/readout_ip_9" BEL "u_sru_cmd_par/readout_ip_8" BEL "u_sru_cmd_par/readout_ip_7" BEL "u_sru_cmd_par/readout_ip_6" BEL "u_sru_cmd_par/readout_ip_5" BEL "u_sru_cmd_par/readout_ip_4" BEL "u_sru_cmd_par/readout_ip_3" BEL "u_sru_cmd_par/readout_ip_2" BEL "u_sru_cmd_par/readout_ip_1" BEL "u_sru_cmd_par/readout_ip_0" BEL "u_sru_cmd_par/SruMonAddr_6" BEL "u_sru_cmd_par/SruMonAddr_5" BEL "u_sru_cmd_par/SruMonAddr_4" BEL "u_sru_cmd_par/SruMonAddr_3" BEL "u_sru_cmd_par/SruMonAddr_2" BEL "u_sru_cmd_par/SruMonAddr_1" BEL "u_sru_cmd_par/SruMonAddr_0" BEL "u_sru_cmd_par/srucfg_31" BEL "u_sru_cmd_par/srucfg_30" BEL "u_sru_cmd_par/srucfg_29" BEL "u_sru_cmd_par/srucfg_28" BEL "u_sru_cmd_par/srucfg_27" BEL "u_sru_cmd_par/srucfg_26" BEL "u_sru_cmd_par/srucfg_25" BEL "u_sru_cmd_par/srucfg_24" BEL "u_sru_cmd_par/srucfg_23" BEL "u_sru_cmd_par/srucfg_22" BEL "u_sru_cmd_par/srucfg_21" BEL "u_sru_cmd_par/srucfg_20" BEL "u_sru_cmd_par/srucfg_19" BEL "u_sru_cmd_par/srucfg_18" BEL "u_sru_cmd_par/srucfg_17" BEL "u_sru_cmd_par/srucfg_16" BEL "u_sru_cmd_par/srucfg_15" BEL "u_sru_cmd_par/srucfg_14" BEL "u_sru_cmd_par/srucfg_13" BEL "u_sru_cmd_par/srucfg_12" BEL "u_sru_cmd_par/srucfg_11" BEL "u_sru_cmd_par/srucfg_10" BEL "u_sru_cmd_par/srucfg_9" BEL "u_sru_cmd_par/srucfg_8" BEL "u_sru_cmd_par/srucfg_7" BEL "u_sru_cmd_par/srucfg_6" BEL "u_sru_cmd_par/srucfg_5" BEL "u_sru_cmd_par/srucfg_4" BEL "u_sru_cmd_par/srucfg_3" BEL "u_sru_cmd_par/srucfg_2" BEL "u_sru_cmd_par/srucfg_1" BEL "u_sru_cmd_par/srucfg_0" BEL "u_sru_cmd_par/altrocfg_39" BEL "u_sru_cmd_par/altrocfg_38" BEL "u_sru_cmd_par/altrocfg_37" BEL "u_sru_cmd_par/altrocfg_36" BEL "u_sru_cmd_par/altrocfg_35" BEL "u_sru_cmd_par/altrocfg_34" BEL "u_sru_cmd_par/altrocfg_33" BEL "u_sru_cmd_par/altrocfg_32" BEL "u_sru_cmd_par/altrocfg_31" BEL "u_sru_cmd_par/altrocfg_30" BEL "u_sru_cmd_par/altrocfg_29" BEL "u_sru_cmd_par/altrocfg_28" BEL "u_sru_cmd_par/altrocfg_27" BEL "u_sru_cmd_par/altrocfg_26" BEL "u_sru_cmd_par/altrocfg_25" BEL "u_sru_cmd_par/altrocfg_24" BEL "u_sru_cmd_par/altrocfg_23" BEL "u_sru_cmd_par/altrocfg_22" BEL "u_sru_cmd_par/altrocfg_21" BEL "u_sru_cmd_par/altrocfg_20" BEL "u_sru_cmd_par/altrocfg_19" BEL "u_sru_cmd_par/altrocfg_18" BEL "u_sru_cmd_par/altrocfg_17" BEL "u_sru_cmd_par/altrocfg_16" BEL "u_sru_cmd_par/altrocfg_15" BEL "u_sru_cmd_par/altrocfg_14" BEL "u_sru_cmd_par/altrocfg_13" BEL "u_sru_cmd_par/altrocfg_12" BEL "u_sru_cmd_par/altrocfg_11" BEL "u_sru_cmd_par/altrocfg_10" BEL "u_sru_cmd_par/altrocfg_9" BEL "u_sru_cmd_par/altrocfg_8" BEL "u_sru_cmd_par/altrocfg_7" BEL "u_sru_cmd_par/altrocfg_6" BEL "u_sru_cmd_par/altrocfg_5" BEL "u_sru_cmd_par/altrocfg_4" BEL "u_sru_cmd_par/altrocfg_3" BEL "u_sru_cmd_par/altrocfg_2" BEL "u_sru_cmd_par/altrocfg_1" BEL "u_sru_cmd_par/altrocfg_0" BEL "u_sru_cmd_par/dtc_rdo_mask_i_39" BEL "u_sru_cmd_par/dtc_rdo_mask_i_38" BEL "u_sru_cmd_par/dtc_rdo_mask_i_37" BEL "u_sru_cmd_par/dtc_rdo_mask_i_36" BEL "u_sru_cmd_par/dtc_rdo_mask_i_35" BEL "u_sru_cmd_par/dtc_rdo_mask_i_34" BEL "u_sru_cmd_par/dtc_rdo_mask_i_33" BEL "u_sru_cmd_par/dtc_rdo_mask_i_32" BEL "u_sru_cmd_par/dtc_rdo_mask_i_31" BEL "u_sru_cmd_par/dtc_rdo_mask_i_30" BEL "u_sru_cmd_par/dtc_rdo_mask_i_29" BEL "u_sru_cmd_par/dtc_rdo_mask_i_28" BEL "u_sru_cmd_par/dtc_rdo_mask_i_27" BEL "u_sru_cmd_par/dtc_rdo_mask_i_26" BEL "u_sru_cmd_par/dtc_rdo_mask_i_25" BEL "u_sru_cmd_par/dtc_rdo_mask_i_24" BEL "u_sru_cmd_par/dtc_rdo_mask_i_23" BEL "u_sru_cmd_par/dtc_rdo_mask_i_22" BEL "u_sru_cmd_par/dtc_rdo_mask_i_21" BEL "u_sru_cmd_par/dtc_rdo_mask_i_20" BEL "u_sru_cmd_par/dtc_rdo_mask_i_19" BEL "u_sru_cmd_par/dtc_rdo_mask_i_18" BEL "u_sru_cmd_par/dtc_rdo_mask_i_17" BEL "u_sru_cmd_par/dtc_rdo_mask_i_16" BEL "u_sru_cmd_par/dtc_rdo_mask_i_15" BEL "u_sru_cmd_par/dtc_rdo_mask_i_14" BEL "u_sru_cmd_par/dtc_rdo_mask_i_13" BEL "u_sru_cmd_par/dtc_rdo_mask_i_12" BEL "u_sru_cmd_par/dtc_rdo_mask_i_11" BEL "u_sru_cmd_par/dtc_rdo_mask_i_10" BEL "u_sru_cmd_par/dtc_rdo_mask_i_9" BEL "u_sru_cmd_par/dtc_rdo_mask_i_8" BEL "u_sru_cmd_par/dtc_rdo_mask_i_7" BEL "u_sru_cmd_par/dtc_rdo_mask_i_6" BEL "u_sru_cmd_par/dtc_rdo_mask_i_5" BEL "u_sru_cmd_par/dtc_rdo_mask_i_4" BEL "u_sru_cmd_par/dtc_rdo_mask_i_3" BEL "u_sru_cmd_par/dtc_rdo_mask_i_2" BEL "u_sru_cmd_par/dtc_rdo_mask_i_1" BEL "u_sru_cmd_par/dtc_rdo_mask_i_0" BEL "u_sru_cmd_par/rcmd_reply_dv" BEL "u_sru_cmd_par/rcmd_reply_data_31" BEL "u_sru_cmd_par/rcmd_reply_data_30" BEL "u_sru_cmd_par/rcmd_reply_data_29" BEL "u_sru_cmd_par/rcmd_reply_data_28" BEL "u_sru_cmd_par/rcmd_reply_data_27" BEL "u_sru_cmd_par/rcmd_reply_data_26" BEL "u_sru_cmd_par/rcmd_reply_data_25" BEL "u_sru_cmd_par/rcmd_reply_data_24" BEL "u_sru_cmd_par/rcmd_reply_data_23" BEL "u_sru_cmd_par/rcmd_reply_data_22" BEL "u_sru_cmd_par/rcmd_reply_data_21" BEL "u_sru_cmd_par/rcmd_reply_data_20" BEL "u_sru_cmd_par/rcmd_reply_data_19" BEL "u_sru_cmd_par/rcmd_reply_data_18" BEL "u_sru_cmd_par/rcmd_reply_data_17" BEL "u_sru_cmd_par/rcmd_reply_data_16" BEL "u_sru_cmd_par/rcmd_reply_data_15" BEL "u_sru_cmd_par/rcmd_reply_data_14" BEL "u_sru_cmd_par/rcmd_reply_data_13" BEL "u_sru_cmd_par/rcmd_reply_data_12" BEL "u_sru_cmd_par/rcmd_reply_data_11" BEL "u_sru_cmd_par/rcmd_reply_data_10" BEL "u_sru_cmd_par/rcmd_reply_data_9" BEL "u_sru_cmd_par/rcmd_reply_data_8" BEL "u_sru_cmd_par/rcmd_reply_data_7" BEL "u_sru_cmd_par/rcmd_reply_data_6" BEL "u_sru_cmd_par/rcmd_reply_data_5" BEL "u_sru_cmd_par/rcmd_reply_data_4" BEL "u_sru_cmd_par/rcmd_reply_data_3" BEL "u_sru_cmd_par/rcmd_reply_data_2" BEL "u_sru_cmd_par/rcmd_reply_data_1" BEL "u_sru_cmd_par/rcmd_reply_data_0" BEL "u_sru_cmd_par/spill_d" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL 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"u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL 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"u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL 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"u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_cmd_par/FastCmd_i" BEL "u_sru_cmd_par/test_pulse_en" BEL "htrig_d" BEL "spill_sync_d" BEL "sru_trig_synced_out_nim" BEL "u_sru_40dtc_top/DTCRamAllFlag_i" BEL "u_sru_cmd_par/reset_cmd" BEL "u_sru_trigger/tlu_event_number_15" BEL "u_sru_trigger/tlu_event_number_14" BEL "u_sru_trigger/tlu_event_number_13" BEL "u_sru_trigger/tlu_event_number_12" BEL "u_sru_trigger/tlu_event_number_11" BEL "u_sru_trigger/tlu_event_number_10" BEL "u_sru_trigger/tlu_event_number_9" BEL "u_sru_trigger/tlu_event_number_8" BEL "u_sru_trigger/tlu_event_number_7" BEL "u_sru_trigger/tlu_event_number_6" BEL "u_sru_trigger/tlu_event_number_5" BEL "u_sru_trigger/tlu_event_number_4" BEL "u_sru_trigger/tlu_event_number_3" BEL "u_sru_trigger/tlu_event_number_2" BEL "u_sru_trigger/tlu_event_number_1" BEL "u_sru_trigger/tlu_event_number_0" BEL "u_sru_trigger/tlu_event_number_shift_16" BEL "u_sru_trigger/tlu_event_number_shift_15" BEL "u_sru_trigger/tlu_event_number_shift_14" BEL "u_sru_trigger/tlu_event_number_shift_13" BEL "u_sru_trigger/tlu_event_number_shift_12" BEL "u_sru_trigger/tlu_event_number_shift_11" BEL "u_sru_trigger/tlu_event_number_shift_10" BEL "u_sru_trigger/tlu_event_number_shift_9" BEL "u_sru_trigger/tlu_event_number_shift_8" BEL "u_sru_trigger/tlu_event_number_shift_7" BEL "u_sru_trigger/tlu_event_number_shift_6" BEL "u_sru_trigger/tlu_event_number_shift_5" BEL "u_sru_trigger/tlu_event_number_shift_4" BEL "u_sru_trigger/tlu_event_number_shift_3" BEL "u_sru_trigger/tlu_event_number_shift_2" BEL "u_sru_trigger/tlu_event_number_shift_1" BEL "u_sru_trigger/tlu_event_number_shift_0" BEL "u_sru_trigger/u_ttc_decoder/st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/ttc_l1" BEL "u_sru_trigger/u_ttc_decoder/ttc_l0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_31" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_30" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_29" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_28" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_27" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_26" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_25" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_24" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_23" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_22" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_21" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_20" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_19" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_18" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_17" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_16" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_15" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_14" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_13" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_23" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_22" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_21" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_20" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_19" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_18" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_17" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_16" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_15" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_14" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_13" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/ttc_l2r" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/ttc_l2aMesRdy" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_59" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_58" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_57" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_56" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_55" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_54" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_53" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_52" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_51" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_50" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_49" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_48" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_47" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_46" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_45" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_44" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_43" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_42" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_41" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_40" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_39" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_38" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_37" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_36" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_35" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_34" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_33" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_32" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_31" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_30" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_29" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_28" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_27" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_26" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_25" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_24" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_23" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_22" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_21" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_20" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_19" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_18" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_17" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_16" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_15" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_14" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_13" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_12" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_11" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_10" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_9" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_8" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_7" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_6" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_5" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_4" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_3" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_2" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_1" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_0" BEL "u_sru_trigger/u_trig_cnt/event_cnt_29" BEL "u_sru_trigger/u_trig_cnt/event_cnt_28" BEL "u_sru_trigger/u_trig_cnt/event_cnt_27" BEL "u_sru_trigger/u_trig_cnt/event_cnt_26" BEL "u_sru_trigger/u_trig_cnt/event_cnt_25" BEL "u_sru_trigger/u_trig_cnt/event_cnt_24" BEL "u_sru_trigger/u_trig_cnt/event_cnt_23" BEL "u_sru_trigger/u_trig_cnt/event_cnt_22" BEL "u_sru_trigger/u_trig_cnt/event_cnt_21" BEL "u_sru_trigger/u_trig_cnt/event_cnt_20" BEL "u_sru_trigger/u_trig_cnt/event_cnt_19" BEL "u_sru_trigger/u_trig_cnt/event_cnt_18" BEL "u_sru_trigger/u_trig_cnt/event_cnt_17" BEL "u_sru_trigger/u_trig_cnt/event_cnt_16" BEL "u_sru_trigger/u_trig_cnt/event_cnt_15" BEL "u_sru_trigger/u_trig_cnt/event_cnt_14" BEL "u_sru_trigger/u_trig_cnt/event_cnt_13" BEL "u_sru_trigger/u_trig_cnt/event_cnt_12" BEL "u_sru_trigger/u_trig_cnt/event_cnt_11" BEL "u_sru_trigger/u_trig_cnt/event_cnt_10" BEL "u_sru_trigger/u_trig_cnt/event_cnt_9" BEL "u_sru_trigger/u_trig_cnt/event_cnt_8" BEL "u_sru_trigger/u_trig_cnt/event_cnt_7" BEL "u_sru_trigger/u_trig_cnt/event_cnt_6" BEL "u_sru_trigger/u_trig_cnt/event_cnt_5" BEL "u_sru_trigger/u_trig_cnt/event_cnt_4" BEL "u_sru_trigger/u_trig_cnt/event_cnt_3" BEL "u_sru_trigger/u_trig_cnt/event_cnt_2" BEL "u_sru_trigger/u_trig_cnt/event_cnt_1" BEL "u_sru_trigger/u_trig_cnt/event_cnt_0" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_31" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_30" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_29" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_28" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_27" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_26" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_25" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_24" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_23" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_22" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_21" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_20" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_19" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_18" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_17" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_16" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_15" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_14" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_13" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_12" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_11" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_10" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_9" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_8" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_7" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_6" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_5" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_4" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_3" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_2" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_1" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_0" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_31" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_30" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_29" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_28" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_27" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_26" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_25" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_24" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_23" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_22" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_21" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_20" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_19" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_18" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_17" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_16" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_15" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_14" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_13" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_12" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_11" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_10" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_9" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_8" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_7" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_6" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_5" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_4" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_3" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_2" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_1" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_0" BEL "u_sru_trigger/u_trig_cnt/event_countdown_31" BEL "u_sru_trigger/u_trig_cnt/event_countdown_30" BEL "u_sru_trigger/u_trig_cnt/event_countdown_29" BEL "u_sru_trigger/u_trig_cnt/event_countdown_28" BEL "u_sru_trigger/u_trig_cnt/event_countdown_27" BEL "u_sru_trigger/u_trig_cnt/event_countdown_26" BEL "u_sru_trigger/u_trig_cnt/event_countdown_25" BEL "u_sru_trigger/u_trig_cnt/event_countdown_24" BEL "u_sru_trigger/u_trig_cnt/event_countdown_23" BEL "u_sru_trigger/u_trig_cnt/event_countdown_22" BEL "u_sru_trigger/u_trig_cnt/event_countdown_21" BEL "u_sru_trigger/u_trig_cnt/event_countdown_20" BEL "u_sru_trigger/u_trig_cnt/event_countdown_19" BEL "u_sru_trigger/u_trig_cnt/event_countdown_18" BEL "u_sru_trigger/u_trig_cnt/event_countdown_17" BEL "u_sru_trigger/u_trig_cnt/event_countdown_16" BEL "u_sru_trigger/u_trig_cnt/event_countdown_15" BEL "u_sru_trigger/u_trig_cnt/event_countdown_14" BEL "u_sru_trigger/u_trig_cnt/event_countdown_13" BEL "u_sru_trigger/u_trig_cnt/event_countdown_12" BEL "u_sru_trigger/u_trig_cnt/event_countdown_11" BEL "u_sru_trigger/u_trig_cnt/event_countdown_10" BEL "u_sru_trigger/u_trig_cnt/event_countdown_9" BEL "u_sru_trigger/u_trig_cnt/event_countdown_8" BEL "u_sru_trigger/u_trig_cnt/event_countdown_7" BEL "u_sru_trigger/u_trig_cnt/event_countdown_6" BEL "u_sru_trigger/u_trig_cnt/event_countdown_5" BEL "u_sru_trigger/u_trig_cnt/event_countdown_4" BEL "u_sru_trigger/u_trig_cnt/event_countdown_3" BEL "u_sru_trigger/u_trig_cnt/event_countdown_2" BEL "u_sru_trigger/u_trig_cnt/event_countdown_1" BEL "u_sru_trigger/u_trig_cnt/event_countdown_0" BEL "u_sru_trigger/u_trig_cnt/clkcntb_3" BEL "u_sru_trigger/u_trig_cnt/clkcntb_2" BEL "u_sru_trigger/u_trig_cnt/clkcntb_1" BEL "u_sru_trigger/u_trig_cnt/clkcntb_0" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/timestamp_59" BEL "u_sru_trigger/u_trig_cnt/timestamp_58" BEL "u_sru_trigger/u_trig_cnt/timestamp_57" BEL "u_sru_trigger/u_trig_cnt/timestamp_56" BEL "u_sru_trigger/u_trig_cnt/timestamp_55" BEL "u_sru_trigger/u_trig_cnt/timestamp_54" BEL "u_sru_trigger/u_trig_cnt/timestamp_53" BEL "u_sru_trigger/u_trig_cnt/timestamp_52" BEL "u_sru_trigger/u_trig_cnt/timestamp_51" BEL "u_sru_trigger/u_trig_cnt/timestamp_50" BEL "u_sru_trigger/u_trig_cnt/timestamp_49" BEL "u_sru_trigger/u_trig_cnt/timestamp_48" BEL "u_sru_trigger/u_trig_cnt/timestamp_47" BEL "u_sru_trigger/u_trig_cnt/timestamp_46" BEL "u_sru_trigger/u_trig_cnt/timestamp_45" BEL "u_sru_trigger/u_trig_cnt/timestamp_44" BEL "u_sru_trigger/u_trig_cnt/timestamp_43" BEL "u_sru_trigger/u_trig_cnt/timestamp_42" BEL "u_sru_trigger/u_trig_cnt/timestamp_41" BEL "u_sru_trigger/u_trig_cnt/timestamp_40" BEL "u_sru_trigger/u_trig_cnt/timestamp_39" BEL "u_sru_trigger/u_trig_cnt/timestamp_38" BEL "u_sru_trigger/u_trig_cnt/timestamp_37" BEL "u_sru_trigger/u_trig_cnt/timestamp_36" BEL "u_sru_trigger/u_trig_cnt/timestamp_35" BEL "u_sru_trigger/u_trig_cnt/timestamp_34" BEL "u_sru_trigger/u_trig_cnt/timestamp_33" BEL "u_sru_trigger/u_trig_cnt/timestamp_32" BEL "u_sru_trigger/u_trig_cnt/timestamp_31" BEL "u_sru_trigger/u_trig_cnt/timestamp_30" BEL "u_sru_trigger/u_trig_cnt/timestamp_29" BEL "u_sru_trigger/u_trig_cnt/timestamp_28" BEL "u_sru_trigger/u_trig_cnt/timestamp_27" BEL "u_sru_trigger/u_trig_cnt/timestamp_26" BEL "u_sru_trigger/u_trig_cnt/timestamp_25" BEL "u_sru_trigger/u_trig_cnt/timestamp_24" BEL "u_sru_trigger/u_trig_cnt/timestamp_23" BEL "u_sru_trigger/u_trig_cnt/timestamp_22" BEL "u_sru_trigger/u_trig_cnt/timestamp_21" BEL "u_sru_trigger/u_trig_cnt/timestamp_20" BEL "u_sru_trigger/u_trig_cnt/timestamp_19" BEL "u_sru_trigger/u_trig_cnt/timestamp_18" BEL "u_sru_trigger/u_trig_cnt/timestamp_17" BEL "u_sru_trigger/u_trig_cnt/timestamp_16" BEL "u_sru_trigger/u_trig_cnt/timestamp_15" BEL "u_sru_trigger/u_trig_cnt/timestamp_14" BEL "u_sru_trigger/u_trig_cnt/timestamp_13" BEL "u_sru_trigger/u_trig_cnt/timestamp_12" BEL "u_sru_trigger/u_trig_cnt/timestamp_11" BEL "u_sru_trigger/u_trig_cnt/timestamp_10" BEL "u_sru_trigger/u_trig_cnt/timestamp_9" BEL "u_sru_trigger/u_trig_cnt/timestamp_8" BEL "u_sru_trigger/u_trig_cnt/timestamp_7" BEL "u_sru_trigger/u_trig_cnt/timestamp_6" BEL "u_sru_trigger/u_trig_cnt/timestamp_5" BEL "u_sru_trigger/u_trig_cnt/timestamp_4" BEL "u_sru_trigger/u_trig_cnt/timestamp_3" BEL "u_sru_trigger/u_trig_cnt/timestamp_2" BEL "u_sru_trigger/u_trig_cnt/timestamp_1" BEL "u_sru_trigger/u_trig_cnt/timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/abortcmd" BEL "u_sru_trigger/u_trig_cnt/rdocmd" BEL "u_sru_trigger/u_trig_cnt/event_cnt_wr_en" BEL "u_sru_trigger/u_trig_cnt/stc" BEL "u_sru_trigger/u_trig_cnt/stb" BEL "u_sru_trigger/u_trig_cnt/stall_events" BEL "u_sru_trigger/u_trig_cnt/BusyFlag_d" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd4" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_15" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_14" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_13" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_12" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_11" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_10" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_9" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_8" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_7" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_6" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_5" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_4" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_3" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_2" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_1" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_0" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd1" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd2" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd3" BEL "u_sru_trigger/u_test_trig_gen/sta_FSM_FFd1" BEL "u_sru_trigger/u_test_trig_gen/sta_FSM_FFd2" BEL "u_sru_trigger/u_test_trig_gen/test_trig" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_15" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_14" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_13" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_12" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_11" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_10" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_9" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_8" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_7" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_6" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_5" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_4" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_3" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_2" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_1" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_0" BEL "u_sru_trigger/u_test_trig_gen/test_l0" BEL "u_sru_trigger/u_test_trig_gen/test_l2a" BEL "u_sru_trigger/u_test_trig_gen/test_l1" BEL "u_sru_trigger/u_test_trig_gen/l0_trig" BEL "u_sru_trigger/u_test_trig_gen/test_pulse" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd3" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_11" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_10" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_9" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_8" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_7" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_6" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_5" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_4" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_3" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_2" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_1" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_0" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd1" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd4" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd2" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd6" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd7" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd5" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd8" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd9" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd10" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd11" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd13" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd14" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd12" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd16" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd17" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd15" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd18" BEL "u_sru_trigger/u_trig_err_detect/DtcRamClr" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_20" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_19" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_18" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_17" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_16" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_15" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_13" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_11" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_9" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_8" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_7" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_6" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_5" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_4" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_3" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_2" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_1" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_0" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_15" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_14" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_13" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_12" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_11" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_10" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_9" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_8" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_7" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_6" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_5" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_4" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_3" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_2" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_1" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_0" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_5" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_2" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_1" BEL "u_sru_trigger/u_trig_err_detect/abortcmd_c" BEL "u_sru_trigger/u_trig_err_detect/rdocmd_c" BEL "u_sru_trigger/u_trig_err_detect/trig_busy" BEL "u_sru_trigger/u_trig_err_detect/ddl_tx_start_i" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_cmd_par/synch_dcs/o" BEL "u_sru_cmd_par/synch_dcs/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_40/Mshreg_o" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/last_packet_sync_ff_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/Mshreg_last_packet_sync_ff_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_d" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_39" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_38" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_37" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_36" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_35" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_34" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_33" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_32" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_31" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_30" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_29" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_28" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_27" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_26" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_25" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_24" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_23" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_22" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_21" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_20" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_19" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_18" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_17" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_16" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_15" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_14" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_13" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_12" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_11" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_10" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_9" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_8" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/last_packet_sync_ff_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_0" BEL "u_main_clk_gen/TrigIOClkSel" BEL "u_SCLKPhaseDetect/cnt_i_1" BEL "u_SCLKPhaseDetect/cnt_i_0" BEL "u_SCLKPhaseDetect/st_FSM_FFd1" BEL "u_SCLKPhaseDetect/st_FSM_FFd2" BEL "u_SCLKPhaseDetect/sclkphasecnt_1" BEL "u_SCLKPhaseDetect/sclkphasecnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/fifo_rd_en" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_dv" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_15" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_14" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_13" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_12" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_11" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_10" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_9" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_8" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_7" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_6" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_5" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_4" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_3" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_2" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_1" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_0" BEL "u_sru_cmd_par/u_ResetSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_ResetSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_ResetSwitch/pulse_out_i" BEL "u_sru_cmd_par/u_BusyClrSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_BusyClrSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_BusyClrSwitch/pulse_out_i" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/pulse_out_i" BEL "u_sru_cmd_par/usrudcsreplyack/st_FSM_FFd1" BEL "u_sru_cmd_par/usrudcsreplyack/st_FSM_FFd2" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_update" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_63" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_62" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_61" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_60" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_59" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_58" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_57" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_56" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_55" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_54" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_53" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_52" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_51" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_50" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_49" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_48" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_47" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_46" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_45" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_44" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_43" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_42" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_41" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_40" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_39" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_38" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_37" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_36" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_35" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_34" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_33" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_32" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_31" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_30" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_29" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_28" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_27" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_26" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_25" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_24" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_23" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_22" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_21" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_20" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_19" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_18" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_17" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_16" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_15" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_14" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_13" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_12" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_11" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_10" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_9" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_8" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_7" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_6" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_5" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_4" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_3" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_2" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_1" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_0" PIN "u_sru_cmd_par/u_srutempmonitor/SYSMON_INST_pins<10>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<65>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout4_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout3_2 = BEL "htrig_number_d" BEL "spill_sync_dd" BEL "u_sru_40dtc_top/DtcRamFlag_ii_39" BEL "u_sru_40dtc_top/DtcRamFlag_ii_38" BEL "u_sru_40dtc_top/DtcRamFlag_ii_37" BEL "u_sru_40dtc_top/DtcRamFlag_ii_36" BEL "u_sru_40dtc_top/DtcRamFlag_ii_35" BEL "u_sru_40dtc_top/DtcRamFlag_ii_34" BEL "u_sru_40dtc_top/DtcRamFlag_ii_33" BEL "u_sru_40dtc_top/DtcRamFlag_ii_32" BEL "u_sru_40dtc_top/DtcRamFlag_ii_31" BEL "u_sru_40dtc_top/DtcRamFlag_ii_30" BEL "u_sru_40dtc_top/DtcRamFlag_ii_29" BEL "u_sru_40dtc_top/DtcRamFlag_ii_28" BEL "u_sru_40dtc_top/DtcRamFlag_ii_27" BEL "u_sru_40dtc_top/DtcRamFlag_ii_26" BEL "u_sru_40dtc_top/DtcRamFlag_ii_25" BEL "u_sru_40dtc_top/DtcRamFlag_ii_24" BEL "u_sru_40dtc_top/DtcRamFlag_ii_23" BEL "u_sru_40dtc_top/DtcRamFlag_ii_22" BEL "u_sru_40dtc_top/DtcRamFlag_ii_21" BEL "u_sru_40dtc_top/DtcRamFlag_ii_20" BEL "u_sru_40dtc_top/DtcRamFlag_ii_19" BEL "u_sru_40dtc_top/DtcRamFlag_ii_18" BEL "u_sru_40dtc_top/DtcRamFlag_ii_17" BEL "u_sru_40dtc_top/DtcRamFlag_ii_16" BEL "u_sru_40dtc_top/DtcRamFlag_ii_15" BEL "u_sru_40dtc_top/DtcRamFlag_ii_14" BEL "u_sru_40dtc_top/DtcRamFlag_ii_13" BEL "u_sru_40dtc_top/DtcRamFlag_ii_12" BEL "u_sru_40dtc_top/DtcRamFlag_ii_11" BEL "u_sru_40dtc_top/DtcRamFlag_ii_10" BEL "u_sru_40dtc_top/DtcRamFlag_ii_9" BEL "u_sru_40dtc_top/DtcRamFlag_ii_8" BEL "u_sru_40dtc_top/DtcRamFlag_ii_7" BEL "u_sru_40dtc_top/DtcRamFlag_ii_6" BEL "u_sru_40dtc_top/DtcRamFlag_ii_5" BEL "u_sru_40dtc_top/DtcRamFlag_ii_4" BEL "u_sru_40dtc_top/DtcRamFlag_ii_3" BEL "u_sru_40dtc_top/DtcRamFlag_ii_2" BEL "u_sru_40dtc_top/DtcRamFlag_ii_1" BEL "u_sru_40dtc_top/DtcRamFlag_ii_0" BEL "u_sru_40dtc_top/abortcmd_i_39" BEL "u_sru_40dtc_top/abortcmd_i_38" BEL "u_sru_40dtc_top/abortcmd_i_37" BEL "u_sru_40dtc_top/abortcmd_i_36" BEL "u_sru_40dtc_top/abortcmd_i_35" BEL "u_sru_40dtc_top/abortcmd_i_34" BEL "u_sru_40dtc_top/abortcmd_i_33" BEL "u_sru_40dtc_top/abortcmd_i_32" BEL "u_sru_40dtc_top/abortcmd_i_31" BEL "u_sru_40dtc_top/abortcmd_i_30" BEL "u_sru_40dtc_top/abortcmd_i_29" BEL "u_sru_40dtc_top/abortcmd_i_28" BEL "u_sru_40dtc_top/abortcmd_i_27" BEL "u_sru_40dtc_top/abortcmd_i_26" BEL "u_sru_40dtc_top/abortcmd_i_25" BEL "u_sru_40dtc_top/abortcmd_i_24" BEL "u_sru_40dtc_top/abortcmd_i_23" BEL "u_sru_40dtc_top/abortcmd_i_22" BEL "u_sru_40dtc_top/abortcmd_i_21" BEL "u_sru_40dtc_top/abortcmd_i_20" BEL "u_sru_40dtc_top/abortcmd_i_19" BEL "u_sru_40dtc_top/abortcmd_i_18" BEL "u_sru_40dtc_top/abortcmd_i_17" BEL "u_sru_40dtc_top/abortcmd_i_16" BEL "u_sru_40dtc_top/abortcmd_i_15" BEL "u_sru_40dtc_top/abortcmd_i_14" BEL "u_sru_40dtc_top/abortcmd_i_13" BEL "u_sru_40dtc_top/abortcmd_i_12" BEL "u_sru_40dtc_top/abortcmd_i_11" BEL "u_sru_40dtc_top/abortcmd_i_10" BEL "u_sru_40dtc_top/abortcmd_i_9" BEL "u_sru_40dtc_top/abortcmd_i_8" BEL "u_sru_40dtc_top/abortcmd_i_7" BEL "u_sru_40dtc_top/abortcmd_i_6" BEL "u_sru_40dtc_top/abortcmd_i_5" BEL "u_sru_40dtc_top/abortcmd_i_4" BEL "u_sru_40dtc_top/abortcmd_i_3" BEL "u_sru_40dtc_top/abortcmd_i_2" BEL "u_sru_40dtc_top/abortcmd_i_1" BEL "u_sru_40dtc_top/abortcmd_i_0" BEL "u_sru_40dtc_top/DTCEventRdy_i_39" BEL "u_sru_40dtc_top/DTCEventRdy_i_38" BEL "u_sru_40dtc_top/DTCEventRdy_i_37" BEL "u_sru_40dtc_top/DTCEventRdy_i_36" BEL "u_sru_40dtc_top/DTCEventRdy_i_35" BEL "u_sru_40dtc_top/DTCEventRdy_i_34" BEL "u_sru_40dtc_top/DTCEventRdy_i_33" BEL "u_sru_40dtc_top/DTCEventRdy_i_32" BEL "u_sru_40dtc_top/DTCEventRdy_i_31" BEL "u_sru_40dtc_top/DTCEventRdy_i_30" BEL "u_sru_40dtc_top/DTCEventRdy_i_29" BEL "u_sru_40dtc_top/DTCEventRdy_i_28" BEL "u_sru_40dtc_top/DTCEventRdy_i_27" BEL "u_sru_40dtc_top/DTCEventRdy_i_26" BEL "u_sru_40dtc_top/DTCEventRdy_i_25" BEL "u_sru_40dtc_top/DTCEventRdy_i_24" BEL "u_sru_40dtc_top/DTCEventRdy_i_23" BEL "u_sru_40dtc_top/DTCEventRdy_i_22" BEL "u_sru_40dtc_top/DTCEventRdy_i_21" BEL "u_sru_40dtc_top/DTCEventRdy_i_20" BEL "u_sru_40dtc_top/DTCEventRdy_i_19" BEL "u_sru_40dtc_top/DTCEventRdy_i_18" BEL "u_sru_40dtc_top/DTCEventRdy_i_17" BEL "u_sru_40dtc_top/DTCEventRdy_i_16" BEL "u_sru_40dtc_top/DTCEventRdy_i_15" BEL "u_sru_40dtc_top/DTCEventRdy_i_14" BEL "u_sru_40dtc_top/DTCEventRdy_i_13" BEL "u_sru_40dtc_top/DTCEventRdy_i_12" BEL "u_sru_40dtc_top/DTCEventRdy_i_11" BEL "u_sru_40dtc_top/DTCEventRdy_i_10" BEL "u_sru_40dtc_top/DTCEventRdy_i_9" BEL "u_sru_40dtc_top/DTCEventRdy_i_8" BEL "u_sru_40dtc_top/DTCEventRdy_i_7" BEL "u_sru_40dtc_top/DTCEventRdy_i_6" BEL "u_sru_40dtc_top/DTCEventRdy_i_5" BEL "u_sru_40dtc_top/DTCEventRdy_i_4" BEL "u_sru_40dtc_top/DTCEventRdy_i_3" BEL "u_sru_40dtc_top/DTCEventRdy_i_2" BEL "u_sru_40dtc_top/DTCEventRdy_i_1" BEL "u_sru_40dtc_top/DTCEventRdy_i_0" BEL "u_sru_40dtc_top/FeeTrig_i_39" BEL "u_sru_40dtc_top/FeeTrig_i_38" BEL "u_sru_40dtc_top/FeeTrig_i_37" BEL "u_sru_40dtc_top/FeeTrig_i_36" BEL "u_sru_40dtc_top/FeeTrig_i_35" BEL "u_sru_40dtc_top/FeeTrig_i_34" BEL "u_sru_40dtc_top/FeeTrig_i_33" BEL "u_sru_40dtc_top/FeeTrig_i_32" BEL "u_sru_40dtc_top/FeeTrig_i_31" BEL "u_sru_40dtc_top/FeeTrig_i_30" BEL "u_sru_40dtc_top/FeeTrig_i_29" BEL "u_sru_40dtc_top/FeeTrig_i_28" BEL "u_sru_40dtc_top/FeeTrig_i_27" BEL "u_sru_40dtc_top/FeeTrig_i_26" BEL "u_sru_40dtc_top/FeeTrig_i_25" BEL "u_sru_40dtc_top/FeeTrig_i_24" BEL "u_sru_40dtc_top/FeeTrig_i_23" BEL "u_sru_40dtc_top/FeeTrig_i_22" BEL "u_sru_40dtc_top/FeeTrig_i_21" BEL "u_sru_40dtc_top/FeeTrig_i_20" BEL "u_sru_40dtc_top/FeeTrig_i_19" BEL "u_sru_40dtc_top/FeeTrig_i_18" BEL "u_sru_40dtc_top/FeeTrig_i_17" BEL "u_sru_40dtc_top/FeeTrig_i_16" BEL "u_sru_40dtc_top/FeeTrig_i_15" BEL "u_sru_40dtc_top/FeeTrig_i_14" BEL "u_sru_40dtc_top/FeeTrig_i_13" BEL "u_sru_40dtc_top/FeeTrig_i_12" BEL "u_sru_40dtc_top/FeeTrig_i_11" BEL "u_sru_40dtc_top/FeeTrig_i_10" BEL "u_sru_40dtc_top/FeeTrig_i_9" BEL "u_sru_40dtc_top/FeeTrig_i_8" BEL "u_sru_40dtc_top/FeeTrig_i_7" BEL "u_sru_40dtc_top/FeeTrig_i_6" BEL "u_sru_40dtc_top/FeeTrig_i_5" BEL "u_sru_40dtc_top/FeeTrig_i_4" BEL "u_sru_40dtc_top/FeeTrig_i_3" BEL "u_sru_40dtc_top/FeeTrig_i_2" BEL "u_sru_40dtc_top/FeeTrig_i_1" BEL "u_sru_40dtc_top/FeeTrig_i_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/clk_ODELAY" BEL "u_sru_cmd_par/BusyCnt_31" BEL "u_sru_cmd_par/BusyCnt_30" BEL "u_sru_cmd_par/BusyCnt_29" BEL "u_sru_cmd_par/BusyCnt_28" BEL "u_sru_cmd_par/BusyCnt_27" BEL "u_sru_cmd_par/BusyCnt_26" BEL "u_sru_cmd_par/BusyCnt_25" BEL "u_sru_cmd_par/BusyCnt_24" BEL "u_sru_cmd_par/BusyCnt_23" BEL "u_sru_cmd_par/BusyCnt_22" BEL "u_sru_cmd_par/BusyCnt_21" BEL "u_sru_cmd_par/BusyCnt_20" BEL "u_sru_cmd_par/BusyCnt_19" BEL "u_sru_cmd_par/BusyCnt_18" BEL "u_sru_cmd_par/BusyCnt_17" BEL "u_sru_cmd_par/BusyCnt_16" BEL "u_sru_cmd_par/BusyCnt_15" BEL "u_sru_cmd_par/BusyCnt_14" BEL "u_sru_cmd_par/BusyCnt_13" BEL "u_sru_cmd_par/BusyCnt_12" BEL "u_sru_cmd_par/BusyCnt_11" BEL "u_sru_cmd_par/BusyCnt_10" BEL "u_sru_cmd_par/BusyCnt_9" BEL "u_sru_cmd_par/BusyCnt_8" BEL "u_sru_cmd_par/BusyCnt_7" BEL "u_sru_cmd_par/BusyCnt_6" BEL "u_sru_cmd_par/BusyCnt_5" BEL "u_sru_cmd_par/BusyCnt_4" BEL "u_sru_cmd_par/BusyCnt_3" BEL "u_sru_cmd_par/BusyCnt_2" BEL "u_sru_cmd_par/BusyCnt_1" BEL "u_sru_cmd_par/BusyCnt_0" BEL "u_sru_cmd_par/SRUMonData_15" BEL "u_sru_cmd_par/SRUMonData_14" BEL "u_sru_cmd_par/SRUMonData_13" BEL "u_sru_cmd_par/SRUMonData_12" BEL "u_sru_cmd_par/SRUMonData_11" BEL "u_sru_cmd_par/SRUMonData_10" BEL "u_sru_cmd_par/SRUMonData_9" BEL "u_sru_cmd_par/SRUMonData_8" BEL "u_sru_cmd_par/SRUMonData_7" BEL "u_sru_cmd_par/SRUMonData_6" BEL "u_sru_cmd_par/SRUMonData_5" BEL "u_sru_cmd_par/SRUMonData_4" BEL "u_sru_cmd_par/SRUMonData_3" BEL "u_sru_cmd_par/SRUMonData_2" BEL "u_sru_cmd_par/SRUMonData_1" BEL "u_sru_cmd_par/SRUMonData_0" BEL "u_sru_cmd_par/FastCmdCode_7" BEL "u_sru_cmd_par/FastCmdCode_6" BEL "u_sru_cmd_par/FastCmdCode_5" BEL "u_sru_cmd_par/FastCmdCode_4" BEL "u_sru_cmd_par/FastCmdCode_3" BEL "u_sru_cmd_par/FastCmdCode_2" BEL "u_sru_cmd_par/FastCmdCode_1" BEL "u_sru_cmd_par/FastCmdCode_0" BEL "u_sru_cmd_par/walign_reg_31" BEL "u_sru_cmd_par/walign_reg_30" BEL "u_sru_cmd_par/walign_reg_29" BEL "u_sru_cmd_par/walign_reg_28" BEL "u_sru_cmd_par/walign_reg_27" BEL "u_sru_cmd_par/walign_reg_26" BEL "u_sru_cmd_par/walign_reg_25" BEL "u_sru_cmd_par/walign_reg_24" BEL "u_sru_cmd_par/walign_reg_23" BEL "u_sru_cmd_par/walign_reg_22" BEL "u_sru_cmd_par/walign_reg_21" BEL "u_sru_cmd_par/walign_reg_20" BEL "u_sru_cmd_par/walign_reg_19" BEL "u_sru_cmd_par/walign_reg_18" BEL "u_sru_cmd_par/walign_reg_17" BEL "u_sru_cmd_par/walign_reg_16" BEL "u_sru_cmd_par/walign_reg_15" BEL "u_sru_cmd_par/walign_reg_14" BEL "u_sru_cmd_par/walign_reg_13" BEL "u_sru_cmd_par/walign_reg_12" BEL "u_sru_cmd_par/walign_reg_11" BEL "u_sru_cmd_par/walign_reg_10" BEL "u_sru_cmd_par/walign_reg_9" BEL "u_sru_cmd_par/walign_reg_8" BEL "u_sru_cmd_par/walign_reg_7" BEL "u_sru_cmd_par/walign_reg_6" BEL "u_sru_cmd_par/walign_reg_5" BEL "u_sru_cmd_par/walign_reg_4" BEL "u_sru_cmd_par/walign_reg_3" BEL "u_sru_cmd_par/walign_reg_2" BEL "u_sru_cmd_par/walign_reg_1" BEL "u_sru_cmd_par/walign_reg_0" BEL "u_sru_cmd_par/errtest_reg_31" BEL "u_sru_cmd_par/errtest_reg_30" BEL "u_sru_cmd_par/errtest_reg_29" BEL "u_sru_cmd_par/errtest_reg_28" BEL "u_sru_cmd_par/errtest_reg_27" BEL "u_sru_cmd_par/errtest_reg_26" BEL "u_sru_cmd_par/errtest_reg_25" BEL "u_sru_cmd_par/errtest_reg_24" BEL "u_sru_cmd_par/errtest_reg_23" BEL "u_sru_cmd_par/errtest_reg_22" BEL "u_sru_cmd_par/errtest_reg_21" BEL "u_sru_cmd_par/errtest_reg_20" BEL "u_sru_cmd_par/errtest_reg_19" BEL "u_sru_cmd_par/errtest_reg_18" BEL "u_sru_cmd_par/errtest_reg_17" BEL "u_sru_cmd_par/errtest_reg_16" BEL "u_sru_cmd_par/errtest_reg_15" BEL "u_sru_cmd_par/errtest_reg_14" BEL "u_sru_cmd_par/errtest_reg_13" BEL "u_sru_cmd_par/errtest_reg_12" BEL "u_sru_cmd_par/errtest_reg_11" BEL "u_sru_cmd_par/errtest_reg_10" BEL "u_sru_cmd_par/errtest_reg_9" BEL "u_sru_cmd_par/errtest_reg_8" BEL "u_sru_cmd_par/errtest_reg_7" BEL "u_sru_cmd_par/errtest_reg_6" BEL "u_sru_cmd_par/errtest_reg_5" BEL "u_sru_cmd_par/errtest_reg_4" BEL "u_sru_cmd_par/errtest_reg_3" BEL "u_sru_cmd_par/errtest_reg_2" BEL "u_sru_cmd_par/errtest_reg_1" BEL "u_sru_cmd_par/errtest_reg_0" BEL "u_sru_cmd_par/FastCmd_reg_15" BEL "u_sru_cmd_par/FastCmd_reg_14" BEL "u_sru_cmd_par/FastCmd_reg_13" BEL "u_sru_cmd_par/FastCmd_reg_12" BEL "u_sru_cmd_par/FastCmd_reg_11" BEL "u_sru_cmd_par/FastCmd_reg_10" BEL "u_sru_cmd_par/FastCmd_reg_9" BEL "u_sru_cmd_par/FastCmd_reg_8" BEL "u_sru_cmd_par/FastCmd_reg_7" BEL "u_sru_cmd_par/FastCmd_reg_6" BEL "u_sru_cmd_par/FastCmd_reg_5" BEL "u_sru_cmd_par/FastCmd_reg_4" BEL "u_sru_cmd_par/FastCmd_reg_3" BEL "u_sru_cmd_par/FastCmd_reg_2" BEL "u_sru_cmd_par/FastCmd_reg_1" BEL "u_sru_cmd_par/FastCmd_reg_0" BEL "u_sru_cmd_par/dtc_out_phase_cmd" BEL "u_sru_cmd_par/event_countdown_wr_en" BEL "u_sru_cmd_par/timestamp_clr" BEL "u_sru_cmd_par/busyclr_cmd" BEL "u_sru_cmd_par/trigerr_clr" BEL "u_sru_cmd_par/trigcnt_clr" BEL "u_sru_cmd_par/evnt_clr" BEL "u_sru_cmd_par/pscmd" BEL "u_sru_cmd_par/strig_cmd" BEL "u_sru_cmd_par/FPGAReload_i" BEL "u_sru_cmd_par/errtest_cmd" BEL "u_sru_cmd_par/walign_cmd" BEL "u_sru_cmd_par/test_pulse_width_9" BEL "u_sru_cmd_par/test_pulse_width_8" BEL "u_sru_cmd_par/test_pulse_width_7" BEL "u_sru_cmd_par/test_pulse_width_6" BEL "u_sru_cmd_par/test_pulse_width_5" BEL "u_sru_cmd_par/test_pulse_width_4" BEL "u_sru_cmd_par/test_pulse_width_3" BEL "u_sru_cmd_par/test_pulse_width_2" BEL "u_sru_cmd_par/test_pulse_width_1" BEL "u_sru_cmd_par/test_pulse_width_0" BEL "u_sru_cmd_par/testtrigcfg1_31" BEL "u_sru_cmd_par/testtrigcfg1_30" BEL "u_sru_cmd_par/testtrigcfg1_29" BEL "u_sru_cmd_par/testtrigcfg1_28" BEL "u_sru_cmd_par/testtrigcfg1_27" BEL "u_sru_cmd_par/testtrigcfg1_26" BEL "u_sru_cmd_par/testtrigcfg1_25" BEL "u_sru_cmd_par/testtrigcfg1_24" BEL "u_sru_cmd_par/testtrigcfg1_23" BEL "u_sru_cmd_par/testtrigcfg1_22" BEL "u_sru_cmd_par/testtrigcfg1_21" BEL "u_sru_cmd_par/testtrigcfg1_20" BEL "u_sru_cmd_par/testtrigcfg1_19" BEL "u_sru_cmd_par/testtrigcfg1_18" BEL "u_sru_cmd_par/testtrigcfg1_17" BEL "u_sru_cmd_par/testtrigcfg1_16" BEL "u_sru_cmd_par/testtrigcfg1_15" BEL "u_sru_cmd_par/testtrigcfg1_14" BEL "u_sru_cmd_par/testtrigcfg1_13" BEL "u_sru_cmd_par/testtrigcfg1_12" BEL "u_sru_cmd_par/testtrigcfg1_11" BEL "u_sru_cmd_par/testtrigcfg1_10" BEL "u_sru_cmd_par/testtrigcfg1_9" BEL "u_sru_cmd_par/testtrigcfg1_8" BEL "u_sru_cmd_par/testtrigcfg1_7" BEL "u_sru_cmd_par/testtrigcfg1_6" BEL "u_sru_cmd_par/testtrigcfg1_5" BEL "u_sru_cmd_par/testtrigcfg1_4" BEL "u_sru_cmd_par/testtrigcfg1_3" BEL "u_sru_cmd_par/testtrigcfg1_2" BEL "u_sru_cmd_par/testtrigcfg1_1" BEL "u_sru_cmd_par/testtrigcfg1_0" BEL "u_sru_cmd_par/test_pulse_start_15" BEL "u_sru_cmd_par/test_pulse_start_14" BEL "u_sru_cmd_par/test_pulse_start_13" BEL "u_sru_cmd_par/test_pulse_start_12" BEL "u_sru_cmd_par/test_pulse_start_11" BEL "u_sru_cmd_par/test_pulse_start_10" BEL "u_sru_cmd_par/test_pulse_start_9" BEL "u_sru_cmd_par/test_pulse_start_8" BEL "u_sru_cmd_par/test_pulse_start_7" BEL "u_sru_cmd_par/test_pulse_start_6" BEL "u_sru_cmd_par/test_pulse_start_5" BEL "u_sru_cmd_par/test_pulse_start_4" BEL "u_sru_cmd_par/test_pulse_start_3" BEL "u_sru_cmd_par/test_pulse_start_2" BEL "u_sru_cmd_par/test_pulse_start_1" BEL "u_sru_cmd_par/test_pulse_start_0" BEL "u_sru_cmd_par/ptrigcfg_16" BEL "u_sru_cmd_par/ptrigcfg_15" BEL "u_sru_cmd_par/ptrigcfg_14" BEL "u_sru_cmd_par/ptrigcfg_13" BEL "u_sru_cmd_par/ptrigcfg_12" BEL "u_sru_cmd_par/ptrigcfg_11" BEL "u_sru_cmd_par/ptrigcfg_10" BEL "u_sru_cmd_par/ptrigcfg_9" BEL "u_sru_cmd_par/ptrigcfg_8" BEL "u_sru_cmd_par/ptrigcfg_7" BEL "u_sru_cmd_par/ptrigcfg_6" BEL "u_sru_cmd_par/ptrigcfg_5" BEL "u_sru_cmd_par/ptrigcfg_4" BEL "u_sru_cmd_par/ptrigcfg_3" BEL "u_sru_cmd_par/ptrigcfg_2" BEL "u_sru_cmd_par/ptrigcfg_1" BEL "u_sru_cmd_par/ptrigcfg_0" BEL "u_sru_cmd_par/trigl2tw_31" BEL "u_sru_cmd_par/trigl2tw_30" BEL "u_sru_cmd_par/trigl2tw_29" BEL "u_sru_cmd_par/trigl2tw_28" BEL "u_sru_cmd_par/trigl2tw_27" BEL "u_sru_cmd_par/trigl2tw_26" BEL "u_sru_cmd_par/trigl2tw_25" BEL "u_sru_cmd_par/trigl2tw_24" BEL "u_sru_cmd_par/trigl2tw_23" BEL "u_sru_cmd_par/trigl2tw_22" BEL "u_sru_cmd_par/trigl2tw_21" BEL "u_sru_cmd_par/trigl2tw_20" BEL "u_sru_cmd_par/trigl2tw_19" BEL "u_sru_cmd_par/trigl2tw_18" BEL "u_sru_cmd_par/trigl2tw_17" BEL "u_sru_cmd_par/trigl2tw_16" BEL "u_sru_cmd_par/trigl2tw_15" BEL "u_sru_cmd_par/trigl2tw_14" BEL "u_sru_cmd_par/trigl2tw_13" BEL "u_sru_cmd_par/trigl2tw_12" BEL "u_sru_cmd_par/trigl2tw_11" BEL "u_sru_cmd_par/trigl2tw_10" BEL "u_sru_cmd_par/trigl2tw_9" BEL "u_sru_cmd_par/trigl2tw_8" BEL "u_sru_cmd_par/trigl2tw_7" BEL "u_sru_cmd_par/trigl2tw_6" BEL "u_sru_cmd_par/trigl2tw_5" BEL "u_sru_cmd_par/trigl2tw_4" BEL "u_sru_cmd_par/trigl2tw_3" BEL "u_sru_cmd_par/trigl2tw_2" BEL "u_sru_cmd_par/trigl2tw_1" BEL "u_sru_cmd_par/trigl2tw_0" BEL "u_sru_cmd_par/testtrigcfg0_31" BEL "u_sru_cmd_par/testtrigcfg0_30" BEL "u_sru_cmd_par/testtrigcfg0_29" BEL "u_sru_cmd_par/testtrigcfg0_28" BEL "u_sru_cmd_par/testtrigcfg0_27" BEL "u_sru_cmd_par/testtrigcfg0_26" BEL "u_sru_cmd_par/testtrigcfg0_25" BEL "u_sru_cmd_par/testtrigcfg0_24" BEL "u_sru_cmd_par/testtrigcfg0_23" BEL "u_sru_cmd_par/testtrigcfg0_22" BEL "u_sru_cmd_par/testtrigcfg0_21" BEL "u_sru_cmd_par/testtrigcfg0_20" BEL "u_sru_cmd_par/testtrigcfg0_19" BEL "u_sru_cmd_par/testtrigcfg0_18" BEL "u_sru_cmd_par/testtrigcfg0_17" BEL "u_sru_cmd_par/testtrigcfg0_16" BEL "u_sru_cmd_par/testtrigcfg0_15" BEL "u_sru_cmd_par/testtrigcfg0_14" BEL "u_sru_cmd_par/testtrigcfg0_13" BEL "u_sru_cmd_par/testtrigcfg0_12" BEL "u_sru_cmd_par/testtrigcfg0_11" BEL "u_sru_cmd_par/testtrigcfg0_10" BEL "u_sru_cmd_par/testtrigcfg0_9" BEL "u_sru_cmd_par/testtrigcfg0_8" BEL "u_sru_cmd_par/testtrigcfg0_7" BEL "u_sru_cmd_par/testtrigcfg0_6" BEL "u_sru_cmd_par/testtrigcfg0_5" BEL "u_sru_cmd_par/testtrigcfg0_4" BEL "u_sru_cmd_par/testtrigcfg0_3" BEL "u_sru_cmd_par/testtrigcfg0_2" BEL "u_sru_cmd_par/testtrigcfg0_1" BEL "u_sru_cmd_par/testtrigcfg0_0" BEL "u_sru_cmd_par/trigl1tw_31" BEL "u_sru_cmd_par/trigl1tw_30" BEL "u_sru_cmd_par/trigl1tw_29" BEL "u_sru_cmd_par/trigl1tw_28" BEL "u_sru_cmd_par/trigl1tw_27" BEL "u_sru_cmd_par/trigl1tw_26" BEL "u_sru_cmd_par/trigl1tw_25" BEL "u_sru_cmd_par/trigl1tw_24" BEL "u_sru_cmd_par/trigl1tw_23" BEL "u_sru_cmd_par/trigl1tw_22" BEL "u_sru_cmd_par/trigl1tw_21" BEL "u_sru_cmd_par/trigl1tw_20" BEL "u_sru_cmd_par/trigl1tw_19" BEL "u_sru_cmd_par/trigl1tw_18" BEL "u_sru_cmd_par/trigl1tw_17" BEL "u_sru_cmd_par/trigl1tw_16" BEL "u_sru_cmd_par/trigl1tw_15" BEL "u_sru_cmd_par/trigl1tw_14" BEL "u_sru_cmd_par/trigl1tw_13" BEL "u_sru_cmd_par/trigl1tw_12" BEL "u_sru_cmd_par/trigl1tw_11" BEL "u_sru_cmd_par/trigl1tw_10" BEL "u_sru_cmd_par/trigl1tw_9" BEL "u_sru_cmd_par/trigl1tw_8" BEL "u_sru_cmd_par/trigl1tw_7" BEL "u_sru_cmd_par/trigl1tw_6" BEL "u_sru_cmd_par/trigl1tw_5" BEL "u_sru_cmd_par/trigl1tw_4" BEL "u_sru_cmd_par/trigl1tw_3" BEL "u_sru_cmd_par/trigl1tw_2" BEL "u_sru_cmd_par/trigl1tw_1" BEL "u_sru_cmd_par/trigl1tw_0" BEL "u_sru_cmd_par/psscancfg_16" BEL "u_sru_cmd_par/psscancfg_15" BEL "u_sru_cmd_par/psscancfg_14" BEL "u_sru_cmd_par/psscancfg_13" BEL "u_sru_cmd_par/psscancfg_12" BEL "u_sru_cmd_par/psscancfg_11" BEL "u_sru_cmd_par/psscancfg_10" BEL "u_sru_cmd_par/psscancfg_9" BEL "u_sru_cmd_par/psscancfg_8" BEL "u_sru_cmd_par/psscancfg_7" BEL "u_sru_cmd_par/psscancfg_6" BEL "u_sru_cmd_par/psscancfg_5" BEL "u_sru_cmd_par/psscancfg_4" BEL "u_sru_cmd_par/psscancfg_3" BEL "u_sru_cmd_par/psscancfg_2" BEL "u_sru_cmd_par/psscancfg_1" BEL "u_sru_cmd_par/psscancfg_0" BEL "u_sru_cmd_par/dtc_power_en_39" BEL "u_sru_cmd_par/dtc_power_en_38" BEL "u_sru_cmd_par/dtc_power_en_37" BEL "u_sru_cmd_par/dtc_power_en_36" BEL "u_sru_cmd_par/dtc_power_en_35" BEL "u_sru_cmd_par/dtc_power_en_34" BEL "u_sru_cmd_par/dtc_power_en_33" BEL "u_sru_cmd_par/dtc_power_en_32" BEL "u_sru_cmd_par/dtc_power_en_31" BEL "u_sru_cmd_par/dtc_power_en_30" BEL "u_sru_cmd_par/dtc_power_en_29" BEL "u_sru_cmd_par/dtc_power_en_28" BEL "u_sru_cmd_par/dtc_power_en_27" BEL "u_sru_cmd_par/dtc_power_en_26" BEL "u_sru_cmd_par/dtc_power_en_25" BEL "u_sru_cmd_par/dtc_power_en_24" BEL "u_sru_cmd_par/dtc_power_en_23" BEL "u_sru_cmd_par/dtc_power_en_22" BEL "u_sru_cmd_par/dtc_power_en_21" BEL "u_sru_cmd_par/dtc_power_en_20" BEL "u_sru_cmd_par/dtc_power_en_19" BEL "u_sru_cmd_par/dtc_power_en_18" BEL "u_sru_cmd_par/dtc_power_en_17" BEL "u_sru_cmd_par/dtc_power_en_16" BEL "u_sru_cmd_par/dtc_power_en_15" BEL "u_sru_cmd_par/dtc_power_en_14" BEL "u_sru_cmd_par/dtc_power_en_13" BEL "u_sru_cmd_par/dtc_power_en_12" BEL "u_sru_cmd_par/dtc_power_en_11" BEL "u_sru_cmd_par/dtc_power_en_10" BEL "u_sru_cmd_par/dtc_power_en_9" BEL "u_sru_cmd_par/dtc_power_en_8" BEL "u_sru_cmd_par/dtc_power_en_7" BEL "u_sru_cmd_par/dtc_power_en_6" BEL "u_sru_cmd_par/dtc_power_en_5" BEL "u_sru_cmd_par/dtc_power_en_4" BEL "u_sru_cmd_par/dtc_power_en_3" BEL "u_sru_cmd_par/dtc_power_en_2" BEL "u_sru_cmd_par/dtc_power_en_1" BEL "u_sru_cmd_par/dtc_power_en_0" BEL "u_sru_cmd_par/dtc_out_phase_delay_4" BEL "u_sru_cmd_par/dtc_out_phase_delay_3" BEL "u_sru_cmd_par/dtc_out_phase_delay_2" BEL "u_sru_cmd_par/dtc_out_phase_delay_1" BEL "u_sru_cmd_par/dtc_out_phase_delay_0" BEL "u_sru_cmd_par/dtc_out_phase_channel_5" BEL "u_sru_cmd_par/dtc_out_phase_channel_4" BEL "u_sru_cmd_par/dtc_out_phase_channel_3" BEL "u_sru_cmd_par/dtc_out_phase_channel_2" BEL "u_sru_cmd_par/dtc_out_phase_channel_1" BEL "u_sru_cmd_par/dtc_out_phase_channel_0" BEL "u_sru_cmd_par/event_countdown_input_31" BEL "u_sru_cmd_par/event_countdown_input_30" BEL "u_sru_cmd_par/event_countdown_input_29" BEL "u_sru_cmd_par/event_countdown_input_28" BEL "u_sru_cmd_par/event_countdown_input_27" BEL "u_sru_cmd_par/event_countdown_input_26" BEL "u_sru_cmd_par/event_countdown_input_25" BEL "u_sru_cmd_par/event_countdown_input_24" BEL "u_sru_cmd_par/event_countdown_input_23" BEL "u_sru_cmd_par/event_countdown_input_22" BEL "u_sru_cmd_par/event_countdown_input_21" BEL "u_sru_cmd_par/event_countdown_input_20" BEL "u_sru_cmd_par/event_countdown_input_19" BEL "u_sru_cmd_par/event_countdown_input_18" BEL "u_sru_cmd_par/event_countdown_input_17" BEL "u_sru_cmd_par/event_countdown_input_16" BEL "u_sru_cmd_par/event_countdown_input_15" BEL "u_sru_cmd_par/event_countdown_input_14" BEL "u_sru_cmd_par/event_countdown_input_13" BEL "u_sru_cmd_par/event_countdown_input_12" BEL "u_sru_cmd_par/event_countdown_input_11" BEL "u_sru_cmd_par/event_countdown_input_10" BEL "u_sru_cmd_par/event_countdown_input_9" BEL "u_sru_cmd_par/event_countdown_input_8" BEL "u_sru_cmd_par/event_countdown_input_7" BEL "u_sru_cmd_par/event_countdown_input_6" BEL "u_sru_cmd_par/event_countdown_input_5" BEL "u_sru_cmd_par/event_countdown_input_4" BEL "u_sru_cmd_par/event_countdown_input_3" BEL "u_sru_cmd_par/event_countdown_input_2" BEL "u_sru_cmd_par/event_countdown_input_1" BEL "u_sru_cmd_par/event_countdown_input_0" BEL "u_sru_cmd_par/dtc_mon_sel_5" BEL "u_sru_cmd_par/dtc_mon_sel_4" BEL "u_sru_cmd_par/dtc_mon_sel_3" BEL "u_sru_cmd_par/dtc_mon_sel_2" BEL "u_sru_cmd_par/dtc_mon_sel_1" BEL "u_sru_cmd_par/dtc_mon_sel_0" BEL "u_sru_cmd_par/readout_ip_31" BEL "u_sru_cmd_par/readout_ip_30" BEL "u_sru_cmd_par/readout_ip_29" BEL "u_sru_cmd_par/readout_ip_28" BEL "u_sru_cmd_par/readout_ip_27" BEL "u_sru_cmd_par/readout_ip_26" BEL "u_sru_cmd_par/readout_ip_25" BEL "u_sru_cmd_par/readout_ip_24" BEL "u_sru_cmd_par/readout_ip_23" BEL "u_sru_cmd_par/readout_ip_22" BEL "u_sru_cmd_par/readout_ip_21" BEL "u_sru_cmd_par/readout_ip_20" BEL "u_sru_cmd_par/readout_ip_19" BEL "u_sru_cmd_par/readout_ip_18" BEL "u_sru_cmd_par/readout_ip_17" BEL "u_sru_cmd_par/readout_ip_16" BEL "u_sru_cmd_par/readout_ip_15" BEL "u_sru_cmd_par/readout_ip_14" BEL "u_sru_cmd_par/readout_ip_13" BEL "u_sru_cmd_par/readout_ip_12" BEL "u_sru_cmd_par/readout_ip_11" BEL "u_sru_cmd_par/readout_ip_10" BEL "u_sru_cmd_par/readout_ip_9" BEL "u_sru_cmd_par/readout_ip_8" BEL "u_sru_cmd_par/readout_ip_7" BEL "u_sru_cmd_par/readout_ip_6" BEL "u_sru_cmd_par/readout_ip_5" BEL "u_sru_cmd_par/readout_ip_4" BEL "u_sru_cmd_par/readout_ip_3" BEL "u_sru_cmd_par/readout_ip_2" BEL "u_sru_cmd_par/readout_ip_1" BEL "u_sru_cmd_par/readout_ip_0" BEL "u_sru_cmd_par/SruMonAddr_6" BEL "u_sru_cmd_par/SruMonAddr_5" BEL "u_sru_cmd_par/SruMonAddr_4" BEL "u_sru_cmd_par/SruMonAddr_3" BEL "u_sru_cmd_par/SruMonAddr_2" BEL "u_sru_cmd_par/SruMonAddr_1" BEL "u_sru_cmd_par/SruMonAddr_0" BEL "u_sru_cmd_par/srucfg_31" BEL "u_sru_cmd_par/srucfg_30" BEL "u_sru_cmd_par/srucfg_29" BEL "u_sru_cmd_par/srucfg_28" BEL "u_sru_cmd_par/srucfg_27" BEL "u_sru_cmd_par/srucfg_26" BEL "u_sru_cmd_par/srucfg_25" BEL "u_sru_cmd_par/srucfg_24" BEL "u_sru_cmd_par/srucfg_23" BEL "u_sru_cmd_par/srucfg_22" BEL "u_sru_cmd_par/srucfg_21" BEL "u_sru_cmd_par/srucfg_20" BEL "u_sru_cmd_par/srucfg_19" BEL "u_sru_cmd_par/srucfg_18" BEL "u_sru_cmd_par/srucfg_17" BEL "u_sru_cmd_par/srucfg_16" BEL "u_sru_cmd_par/srucfg_15" BEL "u_sru_cmd_par/srucfg_14" BEL "u_sru_cmd_par/srucfg_13" BEL "u_sru_cmd_par/srucfg_12" BEL "u_sru_cmd_par/srucfg_11" BEL "u_sru_cmd_par/srucfg_10" BEL "u_sru_cmd_par/srucfg_9" BEL "u_sru_cmd_par/srucfg_8" BEL "u_sru_cmd_par/srucfg_7" BEL "u_sru_cmd_par/srucfg_6" BEL "u_sru_cmd_par/srucfg_5" BEL "u_sru_cmd_par/srucfg_4" BEL "u_sru_cmd_par/srucfg_3" BEL "u_sru_cmd_par/srucfg_2" BEL "u_sru_cmd_par/srucfg_1" BEL "u_sru_cmd_par/srucfg_0" BEL "u_sru_cmd_par/altrocfg_39" BEL "u_sru_cmd_par/altrocfg_38" BEL "u_sru_cmd_par/altrocfg_37" BEL "u_sru_cmd_par/altrocfg_36" BEL "u_sru_cmd_par/altrocfg_35" BEL "u_sru_cmd_par/altrocfg_34" BEL "u_sru_cmd_par/altrocfg_33" BEL "u_sru_cmd_par/altrocfg_32" BEL "u_sru_cmd_par/altrocfg_31" BEL "u_sru_cmd_par/altrocfg_30" BEL "u_sru_cmd_par/altrocfg_29" BEL "u_sru_cmd_par/altrocfg_28" BEL "u_sru_cmd_par/altrocfg_27" BEL "u_sru_cmd_par/altrocfg_26" BEL "u_sru_cmd_par/altrocfg_25" BEL "u_sru_cmd_par/altrocfg_24" BEL "u_sru_cmd_par/altrocfg_23" BEL "u_sru_cmd_par/altrocfg_22" BEL "u_sru_cmd_par/altrocfg_21" BEL "u_sru_cmd_par/altrocfg_20" BEL "u_sru_cmd_par/altrocfg_19" BEL "u_sru_cmd_par/altrocfg_18" BEL "u_sru_cmd_par/altrocfg_17" BEL "u_sru_cmd_par/altrocfg_16" BEL "u_sru_cmd_par/altrocfg_15" BEL "u_sru_cmd_par/altrocfg_14" BEL "u_sru_cmd_par/altrocfg_13" BEL "u_sru_cmd_par/altrocfg_12" BEL "u_sru_cmd_par/altrocfg_11" BEL "u_sru_cmd_par/altrocfg_10" BEL "u_sru_cmd_par/altrocfg_9" BEL "u_sru_cmd_par/altrocfg_8" BEL "u_sru_cmd_par/altrocfg_7" BEL "u_sru_cmd_par/altrocfg_6" BEL "u_sru_cmd_par/altrocfg_5" BEL "u_sru_cmd_par/altrocfg_4" BEL "u_sru_cmd_par/altrocfg_3" BEL "u_sru_cmd_par/altrocfg_2" BEL "u_sru_cmd_par/altrocfg_1" BEL "u_sru_cmd_par/altrocfg_0" BEL "u_sru_cmd_par/dtc_rdo_mask_i_39" BEL "u_sru_cmd_par/dtc_rdo_mask_i_38" BEL "u_sru_cmd_par/dtc_rdo_mask_i_37" BEL "u_sru_cmd_par/dtc_rdo_mask_i_36" BEL "u_sru_cmd_par/dtc_rdo_mask_i_35" BEL "u_sru_cmd_par/dtc_rdo_mask_i_34" BEL "u_sru_cmd_par/dtc_rdo_mask_i_33" BEL "u_sru_cmd_par/dtc_rdo_mask_i_32" BEL "u_sru_cmd_par/dtc_rdo_mask_i_31" BEL "u_sru_cmd_par/dtc_rdo_mask_i_30" BEL "u_sru_cmd_par/dtc_rdo_mask_i_29" BEL "u_sru_cmd_par/dtc_rdo_mask_i_28" BEL "u_sru_cmd_par/dtc_rdo_mask_i_27" BEL "u_sru_cmd_par/dtc_rdo_mask_i_26" BEL "u_sru_cmd_par/dtc_rdo_mask_i_25" BEL "u_sru_cmd_par/dtc_rdo_mask_i_24" BEL "u_sru_cmd_par/dtc_rdo_mask_i_23" BEL "u_sru_cmd_par/dtc_rdo_mask_i_22" BEL "u_sru_cmd_par/dtc_rdo_mask_i_21" BEL "u_sru_cmd_par/dtc_rdo_mask_i_20" BEL "u_sru_cmd_par/dtc_rdo_mask_i_19" BEL "u_sru_cmd_par/dtc_rdo_mask_i_18" BEL "u_sru_cmd_par/dtc_rdo_mask_i_17" BEL "u_sru_cmd_par/dtc_rdo_mask_i_16" BEL "u_sru_cmd_par/dtc_rdo_mask_i_15" BEL "u_sru_cmd_par/dtc_rdo_mask_i_14" BEL "u_sru_cmd_par/dtc_rdo_mask_i_13" BEL "u_sru_cmd_par/dtc_rdo_mask_i_12" BEL "u_sru_cmd_par/dtc_rdo_mask_i_11" BEL "u_sru_cmd_par/dtc_rdo_mask_i_10" BEL "u_sru_cmd_par/dtc_rdo_mask_i_9" BEL "u_sru_cmd_par/dtc_rdo_mask_i_8" BEL "u_sru_cmd_par/dtc_rdo_mask_i_7" BEL "u_sru_cmd_par/dtc_rdo_mask_i_6" BEL "u_sru_cmd_par/dtc_rdo_mask_i_5" BEL "u_sru_cmd_par/dtc_rdo_mask_i_4" BEL "u_sru_cmd_par/dtc_rdo_mask_i_3" BEL "u_sru_cmd_par/dtc_rdo_mask_i_2" BEL "u_sru_cmd_par/dtc_rdo_mask_i_1" BEL "u_sru_cmd_par/dtc_rdo_mask_i_0" BEL "u_sru_cmd_par/rcmd_reply_dv" BEL "u_sru_cmd_par/rcmd_reply_data_31" BEL "u_sru_cmd_par/rcmd_reply_data_30" BEL "u_sru_cmd_par/rcmd_reply_data_29" BEL "u_sru_cmd_par/rcmd_reply_data_28" BEL "u_sru_cmd_par/rcmd_reply_data_27" BEL "u_sru_cmd_par/rcmd_reply_data_26" BEL "u_sru_cmd_par/rcmd_reply_data_25" BEL "u_sru_cmd_par/rcmd_reply_data_24" BEL "u_sru_cmd_par/rcmd_reply_data_23" BEL "u_sru_cmd_par/rcmd_reply_data_22" BEL "u_sru_cmd_par/rcmd_reply_data_21" BEL "u_sru_cmd_par/rcmd_reply_data_20" BEL "u_sru_cmd_par/rcmd_reply_data_19" BEL "u_sru_cmd_par/rcmd_reply_data_18" BEL "u_sru_cmd_par/rcmd_reply_data_17" BEL "u_sru_cmd_par/rcmd_reply_data_16" BEL "u_sru_cmd_par/rcmd_reply_data_15" BEL "u_sru_cmd_par/rcmd_reply_data_14" BEL "u_sru_cmd_par/rcmd_reply_data_13" BEL "u_sru_cmd_par/rcmd_reply_data_12" BEL "u_sru_cmd_par/rcmd_reply_data_11" BEL "u_sru_cmd_par/rcmd_reply_data_10" BEL "u_sru_cmd_par/rcmd_reply_data_9" BEL "u_sru_cmd_par/rcmd_reply_data_8" BEL "u_sru_cmd_par/rcmd_reply_data_7" BEL "u_sru_cmd_par/rcmd_reply_data_6" BEL "u_sru_cmd_par/rcmd_reply_data_5" BEL "u_sru_cmd_par/rcmd_reply_data_4" BEL "u_sru_cmd_par/rcmd_reply_data_3" BEL "u_sru_cmd_par/rcmd_reply_data_2" BEL "u_sru_cmd_par/rcmd_reply_data_1" BEL "u_sru_cmd_par/rcmd_reply_data_0" BEL "u_sru_cmd_par/spill_d" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_cmd_par/FastCmd_i" BEL "u_sru_cmd_par/test_pulse_en" BEL "htrig_d" BEL "spill_sync_d" BEL "sru_trig_synced_out_nim" BEL "u_sru_40dtc_top/DTCRamAllFlag_i" BEL "u_sru_cmd_par/reset_cmd" BEL "u_sru_trigger/tlu_event_number_15" BEL "u_sru_trigger/tlu_event_number_14" BEL "u_sru_trigger/tlu_event_number_13" BEL "u_sru_trigger/tlu_event_number_12" BEL "u_sru_trigger/tlu_event_number_11" BEL "u_sru_trigger/tlu_event_number_10" BEL "u_sru_trigger/tlu_event_number_9" BEL "u_sru_trigger/tlu_event_number_8" BEL "u_sru_trigger/tlu_event_number_7" BEL "u_sru_trigger/tlu_event_number_6" BEL "u_sru_trigger/tlu_event_number_5" BEL "u_sru_trigger/tlu_event_number_4" BEL "u_sru_trigger/tlu_event_number_3" BEL "u_sru_trigger/tlu_event_number_2" BEL "u_sru_trigger/tlu_event_number_1" BEL "u_sru_trigger/tlu_event_number_0" BEL "u_sru_trigger/tlu_event_number_shift_16" BEL "u_sru_trigger/tlu_event_number_shift_15" BEL "u_sru_trigger/tlu_event_number_shift_14" BEL "u_sru_trigger/tlu_event_number_shift_13" BEL "u_sru_trigger/tlu_event_number_shift_12" BEL "u_sru_trigger/tlu_event_number_shift_11" BEL "u_sru_trigger/tlu_event_number_shift_10" BEL "u_sru_trigger/tlu_event_number_shift_9" BEL "u_sru_trigger/tlu_event_number_shift_8" BEL "u_sru_trigger/tlu_event_number_shift_7" BEL "u_sru_trigger/tlu_event_number_shift_6" BEL "u_sru_trigger/tlu_event_number_shift_5" BEL "u_sru_trigger/tlu_event_number_shift_4" BEL "u_sru_trigger/tlu_event_number_shift_3" BEL "u_sru_trigger/tlu_event_number_shift_2" BEL "u_sru_trigger/tlu_event_number_shift_1" BEL "u_sru_trigger/tlu_event_number_shift_0" BEL "u_sru_trigger/u_ttc_decoder/st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/ttc_l1" BEL "u_sru_trigger/u_ttc_decoder/ttc_l0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_31" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_30" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_29" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_28" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_27" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_26" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_25" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_24" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_23" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_22" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_21" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_20" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_19" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_18" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_17" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_16" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_15" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_14" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_13" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_23" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_22" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_21" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_20" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_19" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_18" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_17" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_16" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_15" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_14" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_13" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/ttc_l2r" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/ttc_l2aMesRdy" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_59" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_58" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_57" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_56" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_55" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_54" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_53" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_52" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_51" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_50" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_49" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_48" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_47" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_46" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_45" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_44" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_43" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_42" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_41" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_40" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_39" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_38" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_37" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_36" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_35" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_34" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_33" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_32" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_31" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_30" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_29" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_28" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_27" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_26" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_25" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_24" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_23" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_22" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_21" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_20" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_19" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_18" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_17" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_16" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_15" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_14" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_13" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_12" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_11" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_10" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_9" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_8" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_7" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_6" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_5" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_4" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_3" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_2" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_1" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_0" BEL "u_sru_trigger/u_trig_cnt/event_cnt_29" BEL "u_sru_trigger/u_trig_cnt/event_cnt_28" BEL "u_sru_trigger/u_trig_cnt/event_cnt_27" BEL "u_sru_trigger/u_trig_cnt/event_cnt_26" BEL "u_sru_trigger/u_trig_cnt/event_cnt_25" BEL "u_sru_trigger/u_trig_cnt/event_cnt_24" BEL "u_sru_trigger/u_trig_cnt/event_cnt_23" BEL "u_sru_trigger/u_trig_cnt/event_cnt_22" BEL "u_sru_trigger/u_trig_cnt/event_cnt_21" BEL "u_sru_trigger/u_trig_cnt/event_cnt_20" BEL "u_sru_trigger/u_trig_cnt/event_cnt_19" BEL "u_sru_trigger/u_trig_cnt/event_cnt_18" BEL "u_sru_trigger/u_trig_cnt/event_cnt_17" BEL "u_sru_trigger/u_trig_cnt/event_cnt_16" BEL "u_sru_trigger/u_trig_cnt/event_cnt_15" BEL "u_sru_trigger/u_trig_cnt/event_cnt_14" BEL "u_sru_trigger/u_trig_cnt/event_cnt_13" BEL "u_sru_trigger/u_trig_cnt/event_cnt_12" BEL "u_sru_trigger/u_trig_cnt/event_cnt_11" BEL "u_sru_trigger/u_trig_cnt/event_cnt_10" BEL "u_sru_trigger/u_trig_cnt/event_cnt_9" BEL "u_sru_trigger/u_trig_cnt/event_cnt_8" BEL "u_sru_trigger/u_trig_cnt/event_cnt_7" BEL "u_sru_trigger/u_trig_cnt/event_cnt_6" BEL "u_sru_trigger/u_trig_cnt/event_cnt_5" BEL "u_sru_trigger/u_trig_cnt/event_cnt_4" BEL "u_sru_trigger/u_trig_cnt/event_cnt_3" BEL "u_sru_trigger/u_trig_cnt/event_cnt_2" BEL "u_sru_trigger/u_trig_cnt/event_cnt_1" BEL "u_sru_trigger/u_trig_cnt/event_cnt_0" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_31" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_30" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_29" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_28" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_27" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_26" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_25" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_24" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_23" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_22" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_21" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_20" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_19" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_18" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_17" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_16" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_15" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_14" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_13" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_12" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_11" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_10" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_9" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_8" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_7" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_6" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_5" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_4" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_3" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_2" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_1" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_0" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_31" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_30" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_29" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_28" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_27" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_26" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_25" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_24" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_23" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_22" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_21" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_20" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_19" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_18" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_17" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_16" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_15" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_14" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_13" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_12" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_11" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_10" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_9" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_8" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_7" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_6" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_5" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_4" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_3" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_2" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_1" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_0" BEL "u_sru_trigger/u_trig_cnt/event_countdown_31" BEL "u_sru_trigger/u_trig_cnt/event_countdown_30" BEL "u_sru_trigger/u_trig_cnt/event_countdown_29" BEL "u_sru_trigger/u_trig_cnt/event_countdown_28" BEL "u_sru_trigger/u_trig_cnt/event_countdown_27" BEL "u_sru_trigger/u_trig_cnt/event_countdown_26" BEL "u_sru_trigger/u_trig_cnt/event_countdown_25" BEL "u_sru_trigger/u_trig_cnt/event_countdown_24" BEL "u_sru_trigger/u_trig_cnt/event_countdown_23" BEL "u_sru_trigger/u_trig_cnt/event_countdown_22" BEL "u_sru_trigger/u_trig_cnt/event_countdown_21" BEL "u_sru_trigger/u_trig_cnt/event_countdown_20" BEL "u_sru_trigger/u_trig_cnt/event_countdown_19" BEL "u_sru_trigger/u_trig_cnt/event_countdown_18" BEL "u_sru_trigger/u_trig_cnt/event_countdown_17" BEL "u_sru_trigger/u_trig_cnt/event_countdown_16" BEL "u_sru_trigger/u_trig_cnt/event_countdown_15" BEL "u_sru_trigger/u_trig_cnt/event_countdown_14" BEL "u_sru_trigger/u_trig_cnt/event_countdown_13" BEL "u_sru_trigger/u_trig_cnt/event_countdown_12" BEL "u_sru_trigger/u_trig_cnt/event_countdown_11" BEL "u_sru_trigger/u_trig_cnt/event_countdown_10" BEL "u_sru_trigger/u_trig_cnt/event_countdown_9" BEL "u_sru_trigger/u_trig_cnt/event_countdown_8" BEL "u_sru_trigger/u_trig_cnt/event_countdown_7" BEL "u_sru_trigger/u_trig_cnt/event_countdown_6" BEL "u_sru_trigger/u_trig_cnt/event_countdown_5" BEL "u_sru_trigger/u_trig_cnt/event_countdown_4" BEL "u_sru_trigger/u_trig_cnt/event_countdown_3" BEL "u_sru_trigger/u_trig_cnt/event_countdown_2" BEL "u_sru_trigger/u_trig_cnt/event_countdown_1" BEL "u_sru_trigger/u_trig_cnt/event_countdown_0" BEL "u_sru_trigger/u_trig_cnt/clkcntb_3" BEL "u_sru_trigger/u_trig_cnt/clkcntb_2" BEL "u_sru_trigger/u_trig_cnt/clkcntb_1" BEL "u_sru_trigger/u_trig_cnt/clkcntb_0" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/timestamp_59" BEL "u_sru_trigger/u_trig_cnt/timestamp_58" BEL "u_sru_trigger/u_trig_cnt/timestamp_57" BEL "u_sru_trigger/u_trig_cnt/timestamp_56" BEL "u_sru_trigger/u_trig_cnt/timestamp_55" BEL "u_sru_trigger/u_trig_cnt/timestamp_54" BEL "u_sru_trigger/u_trig_cnt/timestamp_53" BEL "u_sru_trigger/u_trig_cnt/timestamp_52" BEL "u_sru_trigger/u_trig_cnt/timestamp_51" BEL "u_sru_trigger/u_trig_cnt/timestamp_50" BEL "u_sru_trigger/u_trig_cnt/timestamp_49" BEL "u_sru_trigger/u_trig_cnt/timestamp_48" BEL "u_sru_trigger/u_trig_cnt/timestamp_47" BEL "u_sru_trigger/u_trig_cnt/timestamp_46" BEL "u_sru_trigger/u_trig_cnt/timestamp_45" BEL "u_sru_trigger/u_trig_cnt/timestamp_44" BEL "u_sru_trigger/u_trig_cnt/timestamp_43" BEL "u_sru_trigger/u_trig_cnt/timestamp_42" BEL "u_sru_trigger/u_trig_cnt/timestamp_41" BEL "u_sru_trigger/u_trig_cnt/timestamp_40" BEL "u_sru_trigger/u_trig_cnt/timestamp_39" BEL "u_sru_trigger/u_trig_cnt/timestamp_38" BEL "u_sru_trigger/u_trig_cnt/timestamp_37" BEL "u_sru_trigger/u_trig_cnt/timestamp_36" BEL "u_sru_trigger/u_trig_cnt/timestamp_35" BEL "u_sru_trigger/u_trig_cnt/timestamp_34" BEL "u_sru_trigger/u_trig_cnt/timestamp_33" BEL "u_sru_trigger/u_trig_cnt/timestamp_32" BEL "u_sru_trigger/u_trig_cnt/timestamp_31" BEL "u_sru_trigger/u_trig_cnt/timestamp_30" BEL "u_sru_trigger/u_trig_cnt/timestamp_29" BEL "u_sru_trigger/u_trig_cnt/timestamp_28" BEL "u_sru_trigger/u_trig_cnt/timestamp_27" BEL "u_sru_trigger/u_trig_cnt/timestamp_26" BEL "u_sru_trigger/u_trig_cnt/timestamp_25" BEL "u_sru_trigger/u_trig_cnt/timestamp_24" BEL "u_sru_trigger/u_trig_cnt/timestamp_23" BEL "u_sru_trigger/u_trig_cnt/timestamp_22" BEL "u_sru_trigger/u_trig_cnt/timestamp_21" BEL "u_sru_trigger/u_trig_cnt/timestamp_20" BEL "u_sru_trigger/u_trig_cnt/timestamp_19" BEL "u_sru_trigger/u_trig_cnt/timestamp_18" BEL "u_sru_trigger/u_trig_cnt/timestamp_17" BEL "u_sru_trigger/u_trig_cnt/timestamp_16" BEL "u_sru_trigger/u_trig_cnt/timestamp_15" BEL "u_sru_trigger/u_trig_cnt/timestamp_14" BEL "u_sru_trigger/u_trig_cnt/timestamp_13" BEL "u_sru_trigger/u_trig_cnt/timestamp_12" BEL "u_sru_trigger/u_trig_cnt/timestamp_11" BEL "u_sru_trigger/u_trig_cnt/timestamp_10" BEL "u_sru_trigger/u_trig_cnt/timestamp_9" BEL "u_sru_trigger/u_trig_cnt/timestamp_8" BEL "u_sru_trigger/u_trig_cnt/timestamp_7" BEL "u_sru_trigger/u_trig_cnt/timestamp_6" BEL "u_sru_trigger/u_trig_cnt/timestamp_5" BEL "u_sru_trigger/u_trig_cnt/timestamp_4" BEL "u_sru_trigger/u_trig_cnt/timestamp_3" BEL "u_sru_trigger/u_trig_cnt/timestamp_2" BEL "u_sru_trigger/u_trig_cnt/timestamp_1" BEL "u_sru_trigger/u_trig_cnt/timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/abortcmd" BEL "u_sru_trigger/u_trig_cnt/rdocmd" BEL "u_sru_trigger/u_trig_cnt/event_cnt_wr_en" BEL "u_sru_trigger/u_trig_cnt/stc" BEL "u_sru_trigger/u_trig_cnt/stb" BEL "u_sru_trigger/u_trig_cnt/stall_events" BEL "u_sru_trigger/u_trig_cnt/BusyFlag_d" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd4" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_15" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_14" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_13" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_12" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_11" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_10" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_9" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_8" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_7" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_6" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_5" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_4" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_3" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_2" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_1" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_0" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd1" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd2" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd3" BEL "u_sru_trigger/u_test_trig_gen/sta_FSM_FFd1" BEL "u_sru_trigger/u_test_trig_gen/sta_FSM_FFd2" BEL "u_sru_trigger/u_test_trig_gen/test_trig" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_15" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_14" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_13" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_12" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_11" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_10" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_9" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_8" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_7" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_6" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_5" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_4" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_3" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_2" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_1" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_0" BEL "u_sru_trigger/u_test_trig_gen/test_l0" BEL "u_sru_trigger/u_test_trig_gen/test_l2a" BEL "u_sru_trigger/u_test_trig_gen/test_l1" BEL "u_sru_trigger/u_test_trig_gen/l0_trig" BEL "u_sru_trigger/u_test_trig_gen/test_pulse" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd3" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_11" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_10" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_9" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_8" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_7" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_6" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_5" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_4" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_3" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_2" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_1" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_0" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd1" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd4" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd2" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd6" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd7" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd5" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd8" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd9" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd10" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd11" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd13" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd14" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd12" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd16" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd17" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd15" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd18" BEL "u_sru_trigger/u_trig_err_detect/DtcRamClr" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_20" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_19" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_18" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_17" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_16" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_15" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_13" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_11" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_9" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_8" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_7" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_6" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_5" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_4" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_3" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_2" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_1" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_0" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_15" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_14" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_13" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_12" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_11" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_10" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_9" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_8" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_7" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_6" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_5" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_4" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_3" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_2" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_1" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_0" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_5" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_2" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_1" BEL "u_sru_trigger/u_trig_err_detect/abortcmd_c" BEL "u_sru_trigger/u_trig_err_detect/rdocmd_c" BEL "u_sru_trigger/u_trig_err_detect/trig_busy" BEL "u_sru_trigger/u_trig_err_detect/ddl_tx_start_i" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_cmd_par/synch_dcs/o" BEL "u_sru_cmd_par/synch_dcs/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_40/Mshreg_o" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/last_packet_sync_ff_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/Mshreg_last_packet_sync_ff_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_d" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_39" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_38" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_37" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_36" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_35" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_34" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_33" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_32" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_31" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_30" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_29" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_28" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_27" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_26" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_25" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_24" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_23" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_22" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_21" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_20" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_19" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_18" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_17" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_16" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_15" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_14" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_13" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_12" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_11" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_10" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_9" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_8" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/last_packet_sync_ff_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_0" BEL "u_main_clk_gen/TrigIOClkSel" BEL "u_SCLKPhaseDetect/cnt_i_1" BEL "u_SCLKPhaseDetect/cnt_i_0" BEL "u_SCLKPhaseDetect/st_FSM_FFd1" BEL "u_SCLKPhaseDetect/st_FSM_FFd2" BEL "u_SCLKPhaseDetect/sclkphasecnt_1" BEL "u_SCLKPhaseDetect/sclkphasecnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/fifo_rd_en" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_dv" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_15" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_14" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_13" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_12" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_11" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_10" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_9" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_8" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_7" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_6" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_5" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_4" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_3" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_2" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_1" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_0" BEL "u_sru_cmd_par/u_ResetSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_ResetSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_ResetSwitch/pulse_out_i" BEL "u_sru_cmd_par/u_BusyClrSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_BusyClrSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_BusyClrSwitch/pulse_out_i" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/pulse_out_i" BEL "u_sru_cmd_par/usrudcsreplyack/st_FSM_FFd1" BEL "u_sru_cmd_par/usrudcsreplyack/st_FSM_FFd2" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_update" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_63" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_62" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_61" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_60" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_59" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_58" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_57" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_56" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_55" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_54" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_53" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_52" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_51" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_50" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_49" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_48" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_47" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_46" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_45" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_44" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_43" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_42" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_41" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_40" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_39" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_38" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_37" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_36" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_35" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_34" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_33" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_32" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_31" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_30" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_29" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_28" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_27" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_26" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_25" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_24" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_23" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_22" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_21" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_20" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_19" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_18" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_17" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_16" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_15" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_14" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_13" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_12" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_11" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_10" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_9" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_8" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_7" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_6" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_5" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_4" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_3" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_2" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_1" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_0" PIN "u_sru_cmd_par/u_srutempmonitor/SYSMON_INST_pins<10>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<65>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout4_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout3_3 = BEL "htrig_number_d" BEL "spill_sync_dd" BEL "u_sru_40dtc_top/DtcRamFlag_ii_39" BEL "u_sru_40dtc_top/DtcRamFlag_ii_38" BEL "u_sru_40dtc_top/DtcRamFlag_ii_37" BEL "u_sru_40dtc_top/DtcRamFlag_ii_36" BEL "u_sru_40dtc_top/DtcRamFlag_ii_35" BEL "u_sru_40dtc_top/DtcRamFlag_ii_34" BEL "u_sru_40dtc_top/DtcRamFlag_ii_33" BEL "u_sru_40dtc_top/DtcRamFlag_ii_32" BEL "u_sru_40dtc_top/DtcRamFlag_ii_31" BEL "u_sru_40dtc_top/DtcRamFlag_ii_30" BEL "u_sru_40dtc_top/DtcRamFlag_ii_29" BEL "u_sru_40dtc_top/DtcRamFlag_ii_28" BEL "u_sru_40dtc_top/DtcRamFlag_ii_27" BEL "u_sru_40dtc_top/DtcRamFlag_ii_26" BEL "u_sru_40dtc_top/DtcRamFlag_ii_25" BEL "u_sru_40dtc_top/DtcRamFlag_ii_24" BEL "u_sru_40dtc_top/DtcRamFlag_ii_23" BEL "u_sru_40dtc_top/DtcRamFlag_ii_22" BEL "u_sru_40dtc_top/DtcRamFlag_ii_21" BEL "u_sru_40dtc_top/DtcRamFlag_ii_20" BEL "u_sru_40dtc_top/DtcRamFlag_ii_19" BEL "u_sru_40dtc_top/DtcRamFlag_ii_18" BEL "u_sru_40dtc_top/DtcRamFlag_ii_17" BEL "u_sru_40dtc_top/DtcRamFlag_ii_16" BEL "u_sru_40dtc_top/DtcRamFlag_ii_15" BEL "u_sru_40dtc_top/DtcRamFlag_ii_14" BEL "u_sru_40dtc_top/DtcRamFlag_ii_13" BEL "u_sru_40dtc_top/DtcRamFlag_ii_12" BEL "u_sru_40dtc_top/DtcRamFlag_ii_11" BEL "u_sru_40dtc_top/DtcRamFlag_ii_10" BEL "u_sru_40dtc_top/DtcRamFlag_ii_9" BEL "u_sru_40dtc_top/DtcRamFlag_ii_8" BEL "u_sru_40dtc_top/DtcRamFlag_ii_7" BEL "u_sru_40dtc_top/DtcRamFlag_ii_6" BEL "u_sru_40dtc_top/DtcRamFlag_ii_5" BEL "u_sru_40dtc_top/DtcRamFlag_ii_4" BEL "u_sru_40dtc_top/DtcRamFlag_ii_3" BEL "u_sru_40dtc_top/DtcRamFlag_ii_2" BEL "u_sru_40dtc_top/DtcRamFlag_ii_1" BEL "u_sru_40dtc_top/DtcRamFlag_ii_0" BEL "u_sru_40dtc_top/abortcmd_i_39" BEL "u_sru_40dtc_top/abortcmd_i_38" BEL "u_sru_40dtc_top/abortcmd_i_37" BEL "u_sru_40dtc_top/abortcmd_i_36" BEL "u_sru_40dtc_top/abortcmd_i_35" BEL "u_sru_40dtc_top/abortcmd_i_34" BEL "u_sru_40dtc_top/abortcmd_i_33" BEL "u_sru_40dtc_top/abortcmd_i_32" BEL "u_sru_40dtc_top/abortcmd_i_31" BEL "u_sru_40dtc_top/abortcmd_i_30" BEL "u_sru_40dtc_top/abortcmd_i_29" BEL "u_sru_40dtc_top/abortcmd_i_28" BEL "u_sru_40dtc_top/abortcmd_i_27" BEL "u_sru_40dtc_top/abortcmd_i_26" BEL "u_sru_40dtc_top/abortcmd_i_25" BEL "u_sru_40dtc_top/abortcmd_i_24" BEL "u_sru_40dtc_top/abortcmd_i_23" BEL "u_sru_40dtc_top/abortcmd_i_22" BEL "u_sru_40dtc_top/abortcmd_i_21" BEL "u_sru_40dtc_top/abortcmd_i_20" BEL "u_sru_40dtc_top/abortcmd_i_19" BEL "u_sru_40dtc_top/abortcmd_i_18" BEL "u_sru_40dtc_top/abortcmd_i_17" BEL "u_sru_40dtc_top/abortcmd_i_16" BEL "u_sru_40dtc_top/abortcmd_i_15" BEL "u_sru_40dtc_top/abortcmd_i_14" BEL "u_sru_40dtc_top/abortcmd_i_13" BEL "u_sru_40dtc_top/abortcmd_i_12" BEL "u_sru_40dtc_top/abortcmd_i_11" BEL "u_sru_40dtc_top/abortcmd_i_10" BEL "u_sru_40dtc_top/abortcmd_i_9" BEL "u_sru_40dtc_top/abortcmd_i_8" BEL "u_sru_40dtc_top/abortcmd_i_7" BEL "u_sru_40dtc_top/abortcmd_i_6" BEL "u_sru_40dtc_top/abortcmd_i_5" BEL "u_sru_40dtc_top/abortcmd_i_4" BEL "u_sru_40dtc_top/abortcmd_i_3" BEL "u_sru_40dtc_top/abortcmd_i_2" BEL "u_sru_40dtc_top/abortcmd_i_1" BEL "u_sru_40dtc_top/abortcmd_i_0" BEL "u_sru_40dtc_top/DTCEventRdy_i_39" BEL "u_sru_40dtc_top/DTCEventRdy_i_38" BEL "u_sru_40dtc_top/DTCEventRdy_i_37" BEL "u_sru_40dtc_top/DTCEventRdy_i_36" BEL "u_sru_40dtc_top/DTCEventRdy_i_35" BEL "u_sru_40dtc_top/DTCEventRdy_i_34" BEL "u_sru_40dtc_top/DTCEventRdy_i_33" BEL "u_sru_40dtc_top/DTCEventRdy_i_32" BEL "u_sru_40dtc_top/DTCEventRdy_i_31" BEL "u_sru_40dtc_top/DTCEventRdy_i_30" BEL "u_sru_40dtc_top/DTCEventRdy_i_29" BEL "u_sru_40dtc_top/DTCEventRdy_i_28" BEL "u_sru_40dtc_top/DTCEventRdy_i_27" BEL "u_sru_40dtc_top/DTCEventRdy_i_26" BEL "u_sru_40dtc_top/DTCEventRdy_i_25" BEL "u_sru_40dtc_top/DTCEventRdy_i_24" BEL "u_sru_40dtc_top/DTCEventRdy_i_23" BEL "u_sru_40dtc_top/DTCEventRdy_i_22" BEL "u_sru_40dtc_top/DTCEventRdy_i_21" BEL "u_sru_40dtc_top/DTCEventRdy_i_20" BEL "u_sru_40dtc_top/DTCEventRdy_i_19" BEL "u_sru_40dtc_top/DTCEventRdy_i_18" BEL "u_sru_40dtc_top/DTCEventRdy_i_17" BEL "u_sru_40dtc_top/DTCEventRdy_i_16" BEL "u_sru_40dtc_top/DTCEventRdy_i_15" BEL "u_sru_40dtc_top/DTCEventRdy_i_14" BEL "u_sru_40dtc_top/DTCEventRdy_i_13" BEL "u_sru_40dtc_top/DTCEventRdy_i_12" BEL "u_sru_40dtc_top/DTCEventRdy_i_11" BEL "u_sru_40dtc_top/DTCEventRdy_i_10" BEL "u_sru_40dtc_top/DTCEventRdy_i_9" BEL "u_sru_40dtc_top/DTCEventRdy_i_8" BEL "u_sru_40dtc_top/DTCEventRdy_i_7" BEL "u_sru_40dtc_top/DTCEventRdy_i_6" BEL "u_sru_40dtc_top/DTCEventRdy_i_5" BEL "u_sru_40dtc_top/DTCEventRdy_i_4" BEL "u_sru_40dtc_top/DTCEventRdy_i_3" BEL "u_sru_40dtc_top/DTCEventRdy_i_2" BEL "u_sru_40dtc_top/DTCEventRdy_i_1" BEL "u_sru_40dtc_top/DTCEventRdy_i_0" BEL "u_sru_40dtc_top/FeeTrig_i_39" BEL "u_sru_40dtc_top/FeeTrig_i_38" BEL "u_sru_40dtc_top/FeeTrig_i_37" BEL "u_sru_40dtc_top/FeeTrig_i_36" BEL "u_sru_40dtc_top/FeeTrig_i_35" BEL "u_sru_40dtc_top/FeeTrig_i_34" BEL "u_sru_40dtc_top/FeeTrig_i_33" BEL "u_sru_40dtc_top/FeeTrig_i_32" BEL "u_sru_40dtc_top/FeeTrig_i_31" BEL "u_sru_40dtc_top/FeeTrig_i_30" BEL "u_sru_40dtc_top/FeeTrig_i_29" BEL "u_sru_40dtc_top/FeeTrig_i_28" BEL "u_sru_40dtc_top/FeeTrig_i_27" BEL "u_sru_40dtc_top/FeeTrig_i_26" BEL "u_sru_40dtc_top/FeeTrig_i_25" BEL "u_sru_40dtc_top/FeeTrig_i_24" BEL "u_sru_40dtc_top/FeeTrig_i_23" BEL "u_sru_40dtc_top/FeeTrig_i_22" BEL "u_sru_40dtc_top/FeeTrig_i_21" BEL "u_sru_40dtc_top/FeeTrig_i_20" BEL "u_sru_40dtc_top/FeeTrig_i_19" BEL "u_sru_40dtc_top/FeeTrig_i_18" BEL "u_sru_40dtc_top/FeeTrig_i_17" BEL "u_sru_40dtc_top/FeeTrig_i_16" BEL "u_sru_40dtc_top/FeeTrig_i_15" BEL "u_sru_40dtc_top/FeeTrig_i_14" BEL "u_sru_40dtc_top/FeeTrig_i_13" BEL "u_sru_40dtc_top/FeeTrig_i_12" BEL "u_sru_40dtc_top/FeeTrig_i_11" BEL "u_sru_40dtc_top/FeeTrig_i_10" BEL "u_sru_40dtc_top/FeeTrig_i_9" BEL "u_sru_40dtc_top/FeeTrig_i_8" BEL "u_sru_40dtc_top/FeeTrig_i_7" BEL "u_sru_40dtc_top/FeeTrig_i_6" BEL "u_sru_40dtc_top/FeeTrig_i_5" BEL "u_sru_40dtc_top/FeeTrig_i_4" BEL "u_sru_40dtc_top/FeeTrig_i_3" BEL "u_sru_40dtc_top/FeeTrig_i_2" BEL "u_sru_40dtc_top/FeeTrig_i_1" BEL "u_sru_40dtc_top/FeeTrig_i_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/clk_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/trig_ODELAY" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/clk_ODELAY" BEL "u_sru_cmd_par/BusyCnt_31" BEL "u_sru_cmd_par/BusyCnt_30" BEL "u_sru_cmd_par/BusyCnt_29" BEL "u_sru_cmd_par/BusyCnt_28" BEL "u_sru_cmd_par/BusyCnt_27" BEL "u_sru_cmd_par/BusyCnt_26" BEL "u_sru_cmd_par/BusyCnt_25" BEL "u_sru_cmd_par/BusyCnt_24" BEL "u_sru_cmd_par/BusyCnt_23" BEL "u_sru_cmd_par/BusyCnt_22" BEL "u_sru_cmd_par/BusyCnt_21" BEL "u_sru_cmd_par/BusyCnt_20" BEL "u_sru_cmd_par/BusyCnt_19" BEL "u_sru_cmd_par/BusyCnt_18" BEL "u_sru_cmd_par/BusyCnt_17" BEL "u_sru_cmd_par/BusyCnt_16" BEL "u_sru_cmd_par/BusyCnt_15" BEL "u_sru_cmd_par/BusyCnt_14" BEL "u_sru_cmd_par/BusyCnt_13" BEL "u_sru_cmd_par/BusyCnt_12" BEL "u_sru_cmd_par/BusyCnt_11" BEL "u_sru_cmd_par/BusyCnt_10" BEL "u_sru_cmd_par/BusyCnt_9" BEL "u_sru_cmd_par/BusyCnt_8" BEL "u_sru_cmd_par/BusyCnt_7" BEL "u_sru_cmd_par/BusyCnt_6" BEL "u_sru_cmd_par/BusyCnt_5" BEL "u_sru_cmd_par/BusyCnt_4" BEL "u_sru_cmd_par/BusyCnt_3" BEL "u_sru_cmd_par/BusyCnt_2" BEL "u_sru_cmd_par/BusyCnt_1" BEL "u_sru_cmd_par/BusyCnt_0" BEL "u_sru_cmd_par/SRUMonData_15" BEL "u_sru_cmd_par/SRUMonData_14" BEL "u_sru_cmd_par/SRUMonData_13" BEL "u_sru_cmd_par/SRUMonData_12" BEL "u_sru_cmd_par/SRUMonData_11" BEL "u_sru_cmd_par/SRUMonData_10" BEL "u_sru_cmd_par/SRUMonData_9" BEL "u_sru_cmd_par/SRUMonData_8" BEL "u_sru_cmd_par/SRUMonData_7" BEL "u_sru_cmd_par/SRUMonData_6" BEL "u_sru_cmd_par/SRUMonData_5" BEL "u_sru_cmd_par/SRUMonData_4" BEL "u_sru_cmd_par/SRUMonData_3" BEL "u_sru_cmd_par/SRUMonData_2" BEL "u_sru_cmd_par/SRUMonData_1" BEL "u_sru_cmd_par/SRUMonData_0" BEL "u_sru_cmd_par/FastCmdCode_7" BEL "u_sru_cmd_par/FastCmdCode_6" BEL "u_sru_cmd_par/FastCmdCode_5" BEL "u_sru_cmd_par/FastCmdCode_4" BEL "u_sru_cmd_par/FastCmdCode_3" BEL "u_sru_cmd_par/FastCmdCode_2" BEL "u_sru_cmd_par/FastCmdCode_1" BEL "u_sru_cmd_par/FastCmdCode_0" BEL "u_sru_cmd_par/walign_reg_31" BEL "u_sru_cmd_par/walign_reg_30" BEL "u_sru_cmd_par/walign_reg_29" BEL "u_sru_cmd_par/walign_reg_28" BEL "u_sru_cmd_par/walign_reg_27" BEL "u_sru_cmd_par/walign_reg_26" BEL "u_sru_cmd_par/walign_reg_25" BEL "u_sru_cmd_par/walign_reg_24" BEL "u_sru_cmd_par/walign_reg_23" BEL "u_sru_cmd_par/walign_reg_22" BEL "u_sru_cmd_par/walign_reg_21" BEL "u_sru_cmd_par/walign_reg_20" BEL "u_sru_cmd_par/walign_reg_19" BEL "u_sru_cmd_par/walign_reg_18" BEL "u_sru_cmd_par/walign_reg_17" BEL "u_sru_cmd_par/walign_reg_16" BEL "u_sru_cmd_par/walign_reg_15" BEL "u_sru_cmd_par/walign_reg_14" BEL "u_sru_cmd_par/walign_reg_13" BEL "u_sru_cmd_par/walign_reg_12" BEL "u_sru_cmd_par/walign_reg_11" BEL "u_sru_cmd_par/walign_reg_10" BEL "u_sru_cmd_par/walign_reg_9" BEL "u_sru_cmd_par/walign_reg_8" BEL "u_sru_cmd_par/walign_reg_7" BEL "u_sru_cmd_par/walign_reg_6" BEL "u_sru_cmd_par/walign_reg_5" BEL "u_sru_cmd_par/walign_reg_4" BEL "u_sru_cmd_par/walign_reg_3" BEL "u_sru_cmd_par/walign_reg_2" BEL "u_sru_cmd_par/walign_reg_1" BEL "u_sru_cmd_par/walign_reg_0" BEL "u_sru_cmd_par/errtest_reg_31" BEL "u_sru_cmd_par/errtest_reg_30" BEL "u_sru_cmd_par/errtest_reg_29" BEL "u_sru_cmd_par/errtest_reg_28" BEL "u_sru_cmd_par/errtest_reg_27" BEL "u_sru_cmd_par/errtest_reg_26" BEL "u_sru_cmd_par/errtest_reg_25" BEL "u_sru_cmd_par/errtest_reg_24" BEL "u_sru_cmd_par/errtest_reg_23" BEL "u_sru_cmd_par/errtest_reg_22" BEL "u_sru_cmd_par/errtest_reg_21" BEL "u_sru_cmd_par/errtest_reg_20" BEL "u_sru_cmd_par/errtest_reg_19" BEL "u_sru_cmd_par/errtest_reg_18" BEL "u_sru_cmd_par/errtest_reg_17" BEL "u_sru_cmd_par/errtest_reg_16" BEL "u_sru_cmd_par/errtest_reg_15" BEL "u_sru_cmd_par/errtest_reg_14" BEL "u_sru_cmd_par/errtest_reg_13" BEL "u_sru_cmd_par/errtest_reg_12" BEL "u_sru_cmd_par/errtest_reg_11" BEL "u_sru_cmd_par/errtest_reg_10" BEL "u_sru_cmd_par/errtest_reg_9" BEL "u_sru_cmd_par/errtest_reg_8" BEL "u_sru_cmd_par/errtest_reg_7" BEL "u_sru_cmd_par/errtest_reg_6" BEL "u_sru_cmd_par/errtest_reg_5" BEL "u_sru_cmd_par/errtest_reg_4" BEL "u_sru_cmd_par/errtest_reg_3" BEL "u_sru_cmd_par/errtest_reg_2" BEL "u_sru_cmd_par/errtest_reg_1" BEL "u_sru_cmd_par/errtest_reg_0" BEL "u_sru_cmd_par/FastCmd_reg_15" BEL "u_sru_cmd_par/FastCmd_reg_14" BEL "u_sru_cmd_par/FastCmd_reg_13" BEL "u_sru_cmd_par/FastCmd_reg_12" BEL "u_sru_cmd_par/FastCmd_reg_11" BEL "u_sru_cmd_par/FastCmd_reg_10" BEL "u_sru_cmd_par/FastCmd_reg_9" BEL "u_sru_cmd_par/FastCmd_reg_8" BEL "u_sru_cmd_par/FastCmd_reg_7" BEL "u_sru_cmd_par/FastCmd_reg_6" BEL "u_sru_cmd_par/FastCmd_reg_5" BEL "u_sru_cmd_par/FastCmd_reg_4" BEL "u_sru_cmd_par/FastCmd_reg_3" BEL "u_sru_cmd_par/FastCmd_reg_2" BEL "u_sru_cmd_par/FastCmd_reg_1" BEL "u_sru_cmd_par/FastCmd_reg_0" BEL "u_sru_cmd_par/dtc_out_phase_cmd" BEL "u_sru_cmd_par/event_countdown_wr_en" BEL "u_sru_cmd_par/timestamp_clr" BEL "u_sru_cmd_par/busyclr_cmd" BEL "u_sru_cmd_par/trigerr_clr" BEL "u_sru_cmd_par/trigcnt_clr" BEL "u_sru_cmd_par/evnt_clr" BEL "u_sru_cmd_par/pscmd" BEL "u_sru_cmd_par/strig_cmd" BEL "u_sru_cmd_par/FPGAReload_i" BEL "u_sru_cmd_par/errtest_cmd" BEL "u_sru_cmd_par/walign_cmd" BEL "u_sru_cmd_par/test_pulse_width_9" BEL "u_sru_cmd_par/test_pulse_width_8" BEL "u_sru_cmd_par/test_pulse_width_7" BEL "u_sru_cmd_par/test_pulse_width_6" BEL "u_sru_cmd_par/test_pulse_width_5" BEL "u_sru_cmd_par/test_pulse_width_4" BEL "u_sru_cmd_par/test_pulse_width_3" BEL "u_sru_cmd_par/test_pulse_width_2" BEL "u_sru_cmd_par/test_pulse_width_1" BEL "u_sru_cmd_par/test_pulse_width_0" BEL "u_sru_cmd_par/testtrigcfg1_31" BEL "u_sru_cmd_par/testtrigcfg1_30" BEL "u_sru_cmd_par/testtrigcfg1_29" BEL "u_sru_cmd_par/testtrigcfg1_28" BEL "u_sru_cmd_par/testtrigcfg1_27" BEL "u_sru_cmd_par/testtrigcfg1_26" BEL "u_sru_cmd_par/testtrigcfg1_25" BEL "u_sru_cmd_par/testtrigcfg1_24" BEL "u_sru_cmd_par/testtrigcfg1_23" BEL "u_sru_cmd_par/testtrigcfg1_22" BEL "u_sru_cmd_par/testtrigcfg1_21" BEL "u_sru_cmd_par/testtrigcfg1_20" BEL "u_sru_cmd_par/testtrigcfg1_19" BEL "u_sru_cmd_par/testtrigcfg1_18" BEL "u_sru_cmd_par/testtrigcfg1_17" BEL "u_sru_cmd_par/testtrigcfg1_16" BEL "u_sru_cmd_par/testtrigcfg1_15" BEL "u_sru_cmd_par/testtrigcfg1_14" BEL "u_sru_cmd_par/testtrigcfg1_13" BEL "u_sru_cmd_par/testtrigcfg1_12" BEL "u_sru_cmd_par/testtrigcfg1_11" BEL "u_sru_cmd_par/testtrigcfg1_10" BEL "u_sru_cmd_par/testtrigcfg1_9" BEL "u_sru_cmd_par/testtrigcfg1_8" BEL "u_sru_cmd_par/testtrigcfg1_7" BEL "u_sru_cmd_par/testtrigcfg1_6" BEL "u_sru_cmd_par/testtrigcfg1_5" BEL "u_sru_cmd_par/testtrigcfg1_4" BEL "u_sru_cmd_par/testtrigcfg1_3" BEL "u_sru_cmd_par/testtrigcfg1_2" BEL "u_sru_cmd_par/testtrigcfg1_1" BEL "u_sru_cmd_par/testtrigcfg1_0" BEL "u_sru_cmd_par/test_pulse_start_15" BEL "u_sru_cmd_par/test_pulse_start_14" BEL "u_sru_cmd_par/test_pulse_start_13" BEL "u_sru_cmd_par/test_pulse_start_12" BEL "u_sru_cmd_par/test_pulse_start_11" BEL "u_sru_cmd_par/test_pulse_start_10" BEL "u_sru_cmd_par/test_pulse_start_9" BEL "u_sru_cmd_par/test_pulse_start_8" BEL "u_sru_cmd_par/test_pulse_start_7" BEL "u_sru_cmd_par/test_pulse_start_6" BEL "u_sru_cmd_par/test_pulse_start_5" BEL "u_sru_cmd_par/test_pulse_start_4" BEL "u_sru_cmd_par/test_pulse_start_3" BEL "u_sru_cmd_par/test_pulse_start_2" BEL "u_sru_cmd_par/test_pulse_start_1" BEL "u_sru_cmd_par/test_pulse_start_0" BEL "u_sru_cmd_par/ptrigcfg_16" BEL "u_sru_cmd_par/ptrigcfg_15" BEL "u_sru_cmd_par/ptrigcfg_14" BEL "u_sru_cmd_par/ptrigcfg_13" BEL "u_sru_cmd_par/ptrigcfg_12" BEL "u_sru_cmd_par/ptrigcfg_11" BEL "u_sru_cmd_par/ptrigcfg_10" BEL "u_sru_cmd_par/ptrigcfg_9" BEL "u_sru_cmd_par/ptrigcfg_8" BEL "u_sru_cmd_par/ptrigcfg_7" BEL "u_sru_cmd_par/ptrigcfg_6" BEL "u_sru_cmd_par/ptrigcfg_5" BEL "u_sru_cmd_par/ptrigcfg_4" BEL "u_sru_cmd_par/ptrigcfg_3" BEL "u_sru_cmd_par/ptrigcfg_2" BEL "u_sru_cmd_par/ptrigcfg_1" BEL "u_sru_cmd_par/ptrigcfg_0" BEL "u_sru_cmd_par/trigl2tw_31" BEL "u_sru_cmd_par/trigl2tw_30" BEL "u_sru_cmd_par/trigl2tw_29" BEL "u_sru_cmd_par/trigl2tw_28" BEL "u_sru_cmd_par/trigl2tw_27" BEL "u_sru_cmd_par/trigl2tw_26" BEL "u_sru_cmd_par/trigl2tw_25" BEL "u_sru_cmd_par/trigl2tw_24" BEL "u_sru_cmd_par/trigl2tw_23" BEL "u_sru_cmd_par/trigl2tw_22" BEL "u_sru_cmd_par/trigl2tw_21" BEL "u_sru_cmd_par/trigl2tw_20" BEL "u_sru_cmd_par/trigl2tw_19" BEL "u_sru_cmd_par/trigl2tw_18" BEL "u_sru_cmd_par/trigl2tw_17" BEL "u_sru_cmd_par/trigl2tw_16" BEL "u_sru_cmd_par/trigl2tw_15" BEL "u_sru_cmd_par/trigl2tw_14" BEL "u_sru_cmd_par/trigl2tw_13" BEL "u_sru_cmd_par/trigl2tw_12" BEL "u_sru_cmd_par/trigl2tw_11" BEL "u_sru_cmd_par/trigl2tw_10" BEL "u_sru_cmd_par/trigl2tw_9" BEL "u_sru_cmd_par/trigl2tw_8" BEL "u_sru_cmd_par/trigl2tw_7" BEL "u_sru_cmd_par/trigl2tw_6" BEL "u_sru_cmd_par/trigl2tw_5" BEL "u_sru_cmd_par/trigl2tw_4" BEL "u_sru_cmd_par/trigl2tw_3" BEL "u_sru_cmd_par/trigl2tw_2" BEL "u_sru_cmd_par/trigl2tw_1" BEL "u_sru_cmd_par/trigl2tw_0" BEL "u_sru_cmd_par/testtrigcfg0_31" BEL "u_sru_cmd_par/testtrigcfg0_30" BEL "u_sru_cmd_par/testtrigcfg0_29" BEL "u_sru_cmd_par/testtrigcfg0_28" BEL "u_sru_cmd_par/testtrigcfg0_27" BEL "u_sru_cmd_par/testtrigcfg0_26" BEL "u_sru_cmd_par/testtrigcfg0_25" BEL "u_sru_cmd_par/testtrigcfg0_24" BEL "u_sru_cmd_par/testtrigcfg0_23" BEL "u_sru_cmd_par/testtrigcfg0_22" BEL "u_sru_cmd_par/testtrigcfg0_21" BEL "u_sru_cmd_par/testtrigcfg0_20" BEL "u_sru_cmd_par/testtrigcfg0_19" BEL "u_sru_cmd_par/testtrigcfg0_18" BEL "u_sru_cmd_par/testtrigcfg0_17" BEL "u_sru_cmd_par/testtrigcfg0_16" BEL "u_sru_cmd_par/testtrigcfg0_15" BEL "u_sru_cmd_par/testtrigcfg0_14" BEL "u_sru_cmd_par/testtrigcfg0_13" BEL "u_sru_cmd_par/testtrigcfg0_12" BEL "u_sru_cmd_par/testtrigcfg0_11" BEL "u_sru_cmd_par/testtrigcfg0_10" BEL "u_sru_cmd_par/testtrigcfg0_9" BEL "u_sru_cmd_par/testtrigcfg0_8" BEL "u_sru_cmd_par/testtrigcfg0_7" BEL "u_sru_cmd_par/testtrigcfg0_6" BEL "u_sru_cmd_par/testtrigcfg0_5" BEL "u_sru_cmd_par/testtrigcfg0_4" BEL "u_sru_cmd_par/testtrigcfg0_3" BEL "u_sru_cmd_par/testtrigcfg0_2" BEL "u_sru_cmd_par/testtrigcfg0_1" BEL "u_sru_cmd_par/testtrigcfg0_0" BEL "u_sru_cmd_par/trigl1tw_31" BEL "u_sru_cmd_par/trigl1tw_30" BEL "u_sru_cmd_par/trigl1tw_29" BEL "u_sru_cmd_par/trigl1tw_28" BEL "u_sru_cmd_par/trigl1tw_27" BEL "u_sru_cmd_par/trigl1tw_26" BEL "u_sru_cmd_par/trigl1tw_25" BEL "u_sru_cmd_par/trigl1tw_24" BEL "u_sru_cmd_par/trigl1tw_23" BEL "u_sru_cmd_par/trigl1tw_22" BEL "u_sru_cmd_par/trigl1tw_21" BEL "u_sru_cmd_par/trigl1tw_20" BEL "u_sru_cmd_par/trigl1tw_19" BEL "u_sru_cmd_par/trigl1tw_18" BEL "u_sru_cmd_par/trigl1tw_17" BEL "u_sru_cmd_par/trigl1tw_16" BEL "u_sru_cmd_par/trigl1tw_15" BEL "u_sru_cmd_par/trigl1tw_14" BEL "u_sru_cmd_par/trigl1tw_13" BEL "u_sru_cmd_par/trigl1tw_12" BEL "u_sru_cmd_par/trigl1tw_11" BEL "u_sru_cmd_par/trigl1tw_10" BEL "u_sru_cmd_par/trigl1tw_9" BEL "u_sru_cmd_par/trigl1tw_8" BEL "u_sru_cmd_par/trigl1tw_7" BEL "u_sru_cmd_par/trigl1tw_6" BEL "u_sru_cmd_par/trigl1tw_5" BEL "u_sru_cmd_par/trigl1tw_4" BEL "u_sru_cmd_par/trigl1tw_3" BEL "u_sru_cmd_par/trigl1tw_2" BEL "u_sru_cmd_par/trigl1tw_1" BEL "u_sru_cmd_par/trigl1tw_0" BEL "u_sru_cmd_par/psscancfg_16" BEL "u_sru_cmd_par/psscancfg_15" BEL "u_sru_cmd_par/psscancfg_14" BEL "u_sru_cmd_par/psscancfg_13" BEL "u_sru_cmd_par/psscancfg_12" BEL "u_sru_cmd_par/psscancfg_11" BEL "u_sru_cmd_par/psscancfg_10" BEL "u_sru_cmd_par/psscancfg_9" BEL "u_sru_cmd_par/psscancfg_8" BEL "u_sru_cmd_par/psscancfg_7" BEL "u_sru_cmd_par/psscancfg_6" BEL "u_sru_cmd_par/psscancfg_5" BEL "u_sru_cmd_par/psscancfg_4" BEL "u_sru_cmd_par/psscancfg_3" BEL "u_sru_cmd_par/psscancfg_2" BEL "u_sru_cmd_par/psscancfg_1" BEL "u_sru_cmd_par/psscancfg_0" BEL "u_sru_cmd_par/dtc_power_en_39" BEL "u_sru_cmd_par/dtc_power_en_38" BEL "u_sru_cmd_par/dtc_power_en_37" BEL "u_sru_cmd_par/dtc_power_en_36" BEL "u_sru_cmd_par/dtc_power_en_35" BEL "u_sru_cmd_par/dtc_power_en_34" BEL "u_sru_cmd_par/dtc_power_en_33" BEL "u_sru_cmd_par/dtc_power_en_32" BEL "u_sru_cmd_par/dtc_power_en_31" BEL "u_sru_cmd_par/dtc_power_en_30" BEL "u_sru_cmd_par/dtc_power_en_29" BEL "u_sru_cmd_par/dtc_power_en_28" BEL "u_sru_cmd_par/dtc_power_en_27" BEL "u_sru_cmd_par/dtc_power_en_26" BEL "u_sru_cmd_par/dtc_power_en_25" BEL "u_sru_cmd_par/dtc_power_en_24" BEL "u_sru_cmd_par/dtc_power_en_23" BEL "u_sru_cmd_par/dtc_power_en_22" BEL "u_sru_cmd_par/dtc_power_en_21" BEL "u_sru_cmd_par/dtc_power_en_20" BEL "u_sru_cmd_par/dtc_power_en_19" BEL "u_sru_cmd_par/dtc_power_en_18" BEL "u_sru_cmd_par/dtc_power_en_17" BEL "u_sru_cmd_par/dtc_power_en_16" BEL "u_sru_cmd_par/dtc_power_en_15" BEL "u_sru_cmd_par/dtc_power_en_14" BEL "u_sru_cmd_par/dtc_power_en_13" BEL "u_sru_cmd_par/dtc_power_en_12" BEL "u_sru_cmd_par/dtc_power_en_11" BEL "u_sru_cmd_par/dtc_power_en_10" BEL "u_sru_cmd_par/dtc_power_en_9" BEL "u_sru_cmd_par/dtc_power_en_8" BEL "u_sru_cmd_par/dtc_power_en_7" BEL "u_sru_cmd_par/dtc_power_en_6" BEL "u_sru_cmd_par/dtc_power_en_5" BEL "u_sru_cmd_par/dtc_power_en_4" BEL "u_sru_cmd_par/dtc_power_en_3" BEL "u_sru_cmd_par/dtc_power_en_2" BEL "u_sru_cmd_par/dtc_power_en_1" BEL "u_sru_cmd_par/dtc_power_en_0" BEL "u_sru_cmd_par/dtc_out_phase_delay_4" BEL "u_sru_cmd_par/dtc_out_phase_delay_3" BEL "u_sru_cmd_par/dtc_out_phase_delay_2" BEL "u_sru_cmd_par/dtc_out_phase_delay_1" BEL "u_sru_cmd_par/dtc_out_phase_delay_0" BEL "u_sru_cmd_par/dtc_out_phase_channel_5" BEL "u_sru_cmd_par/dtc_out_phase_channel_4" BEL "u_sru_cmd_par/dtc_out_phase_channel_3" BEL "u_sru_cmd_par/dtc_out_phase_channel_2" BEL "u_sru_cmd_par/dtc_out_phase_channel_1" BEL "u_sru_cmd_par/dtc_out_phase_channel_0" BEL "u_sru_cmd_par/event_countdown_input_31" BEL "u_sru_cmd_par/event_countdown_input_30" BEL "u_sru_cmd_par/event_countdown_input_29" BEL "u_sru_cmd_par/event_countdown_input_28" BEL "u_sru_cmd_par/event_countdown_input_27" BEL "u_sru_cmd_par/event_countdown_input_26" BEL "u_sru_cmd_par/event_countdown_input_25" BEL "u_sru_cmd_par/event_countdown_input_24" BEL "u_sru_cmd_par/event_countdown_input_23" BEL "u_sru_cmd_par/event_countdown_input_22" BEL "u_sru_cmd_par/event_countdown_input_21" BEL "u_sru_cmd_par/event_countdown_input_20" BEL "u_sru_cmd_par/event_countdown_input_19" BEL "u_sru_cmd_par/event_countdown_input_18" BEL "u_sru_cmd_par/event_countdown_input_17" BEL "u_sru_cmd_par/event_countdown_input_16" BEL "u_sru_cmd_par/event_countdown_input_15" BEL "u_sru_cmd_par/event_countdown_input_14" BEL "u_sru_cmd_par/event_countdown_input_13" BEL "u_sru_cmd_par/event_countdown_input_12" BEL "u_sru_cmd_par/event_countdown_input_11" BEL "u_sru_cmd_par/event_countdown_input_10" BEL "u_sru_cmd_par/event_countdown_input_9" BEL "u_sru_cmd_par/event_countdown_input_8" BEL "u_sru_cmd_par/event_countdown_input_7" BEL "u_sru_cmd_par/event_countdown_input_6" BEL "u_sru_cmd_par/event_countdown_input_5" BEL "u_sru_cmd_par/event_countdown_input_4" BEL "u_sru_cmd_par/event_countdown_input_3" BEL "u_sru_cmd_par/event_countdown_input_2" BEL "u_sru_cmd_par/event_countdown_input_1" BEL "u_sru_cmd_par/event_countdown_input_0" BEL "u_sru_cmd_par/dtc_mon_sel_5" BEL "u_sru_cmd_par/dtc_mon_sel_4" BEL "u_sru_cmd_par/dtc_mon_sel_3" BEL "u_sru_cmd_par/dtc_mon_sel_2" BEL "u_sru_cmd_par/dtc_mon_sel_1" BEL "u_sru_cmd_par/dtc_mon_sel_0" BEL "u_sru_cmd_par/readout_ip_31" BEL "u_sru_cmd_par/readout_ip_30" BEL "u_sru_cmd_par/readout_ip_29" BEL "u_sru_cmd_par/readout_ip_28" BEL "u_sru_cmd_par/readout_ip_27" BEL "u_sru_cmd_par/readout_ip_26" BEL "u_sru_cmd_par/readout_ip_25" BEL "u_sru_cmd_par/readout_ip_24" BEL "u_sru_cmd_par/readout_ip_23" BEL "u_sru_cmd_par/readout_ip_22" BEL "u_sru_cmd_par/readout_ip_21" BEL "u_sru_cmd_par/readout_ip_20" BEL "u_sru_cmd_par/readout_ip_19" BEL "u_sru_cmd_par/readout_ip_18" BEL "u_sru_cmd_par/readout_ip_17" BEL "u_sru_cmd_par/readout_ip_16" BEL "u_sru_cmd_par/readout_ip_15" BEL "u_sru_cmd_par/readout_ip_14" BEL "u_sru_cmd_par/readout_ip_13" BEL "u_sru_cmd_par/readout_ip_12" BEL "u_sru_cmd_par/readout_ip_11" BEL "u_sru_cmd_par/readout_ip_10" BEL "u_sru_cmd_par/readout_ip_9" BEL "u_sru_cmd_par/readout_ip_8" BEL "u_sru_cmd_par/readout_ip_7" BEL "u_sru_cmd_par/readout_ip_6" BEL "u_sru_cmd_par/readout_ip_5" BEL "u_sru_cmd_par/readout_ip_4" BEL "u_sru_cmd_par/readout_ip_3" BEL "u_sru_cmd_par/readout_ip_2" BEL "u_sru_cmd_par/readout_ip_1" BEL "u_sru_cmd_par/readout_ip_0" BEL "u_sru_cmd_par/SruMonAddr_6" BEL "u_sru_cmd_par/SruMonAddr_5" BEL "u_sru_cmd_par/SruMonAddr_4" BEL "u_sru_cmd_par/SruMonAddr_3" BEL "u_sru_cmd_par/SruMonAddr_2" BEL "u_sru_cmd_par/SruMonAddr_1" BEL "u_sru_cmd_par/SruMonAddr_0" BEL "u_sru_cmd_par/srucfg_31" BEL "u_sru_cmd_par/srucfg_30" BEL "u_sru_cmd_par/srucfg_29" BEL "u_sru_cmd_par/srucfg_28" BEL "u_sru_cmd_par/srucfg_27" BEL "u_sru_cmd_par/srucfg_26" BEL "u_sru_cmd_par/srucfg_25" BEL "u_sru_cmd_par/srucfg_24" BEL "u_sru_cmd_par/srucfg_23" BEL "u_sru_cmd_par/srucfg_22" BEL "u_sru_cmd_par/srucfg_21" BEL "u_sru_cmd_par/srucfg_20" BEL "u_sru_cmd_par/srucfg_19" BEL "u_sru_cmd_par/srucfg_18" BEL "u_sru_cmd_par/srucfg_17" BEL "u_sru_cmd_par/srucfg_16" BEL "u_sru_cmd_par/srucfg_15" BEL "u_sru_cmd_par/srucfg_14" BEL "u_sru_cmd_par/srucfg_13" BEL "u_sru_cmd_par/srucfg_12" BEL "u_sru_cmd_par/srucfg_11" BEL "u_sru_cmd_par/srucfg_10" BEL "u_sru_cmd_par/srucfg_9" BEL "u_sru_cmd_par/srucfg_8" BEL "u_sru_cmd_par/srucfg_7" BEL "u_sru_cmd_par/srucfg_6" BEL "u_sru_cmd_par/srucfg_5" BEL "u_sru_cmd_par/srucfg_4" BEL "u_sru_cmd_par/srucfg_3" BEL "u_sru_cmd_par/srucfg_2" BEL "u_sru_cmd_par/srucfg_1" BEL "u_sru_cmd_par/srucfg_0" BEL "u_sru_cmd_par/altrocfg_39" BEL "u_sru_cmd_par/altrocfg_38" BEL "u_sru_cmd_par/altrocfg_37" BEL "u_sru_cmd_par/altrocfg_36" BEL "u_sru_cmd_par/altrocfg_35" BEL "u_sru_cmd_par/altrocfg_34" BEL "u_sru_cmd_par/altrocfg_33" BEL "u_sru_cmd_par/altrocfg_32" BEL "u_sru_cmd_par/altrocfg_31" BEL "u_sru_cmd_par/altrocfg_30" BEL "u_sru_cmd_par/altrocfg_29" BEL "u_sru_cmd_par/altrocfg_28" BEL "u_sru_cmd_par/altrocfg_27" BEL "u_sru_cmd_par/altrocfg_26" BEL "u_sru_cmd_par/altrocfg_25" BEL "u_sru_cmd_par/altrocfg_24" BEL "u_sru_cmd_par/altrocfg_23" BEL "u_sru_cmd_par/altrocfg_22" BEL "u_sru_cmd_par/altrocfg_21" BEL "u_sru_cmd_par/altrocfg_20" BEL "u_sru_cmd_par/altrocfg_19" BEL "u_sru_cmd_par/altrocfg_18" BEL "u_sru_cmd_par/altrocfg_17" BEL "u_sru_cmd_par/altrocfg_16" BEL "u_sru_cmd_par/altrocfg_15" BEL "u_sru_cmd_par/altrocfg_14" BEL "u_sru_cmd_par/altrocfg_13" BEL "u_sru_cmd_par/altrocfg_12" BEL "u_sru_cmd_par/altrocfg_11" BEL "u_sru_cmd_par/altrocfg_10" BEL "u_sru_cmd_par/altrocfg_9" BEL "u_sru_cmd_par/altrocfg_8" BEL "u_sru_cmd_par/altrocfg_7" BEL "u_sru_cmd_par/altrocfg_6" BEL "u_sru_cmd_par/altrocfg_5" BEL "u_sru_cmd_par/altrocfg_4" BEL "u_sru_cmd_par/altrocfg_3" BEL "u_sru_cmd_par/altrocfg_2" BEL "u_sru_cmd_par/altrocfg_1" BEL "u_sru_cmd_par/altrocfg_0" BEL "u_sru_cmd_par/dtc_rdo_mask_i_39" BEL "u_sru_cmd_par/dtc_rdo_mask_i_38" BEL "u_sru_cmd_par/dtc_rdo_mask_i_37" BEL "u_sru_cmd_par/dtc_rdo_mask_i_36" BEL "u_sru_cmd_par/dtc_rdo_mask_i_35" BEL "u_sru_cmd_par/dtc_rdo_mask_i_34" BEL "u_sru_cmd_par/dtc_rdo_mask_i_33" BEL "u_sru_cmd_par/dtc_rdo_mask_i_32" BEL "u_sru_cmd_par/dtc_rdo_mask_i_31" BEL "u_sru_cmd_par/dtc_rdo_mask_i_30" BEL "u_sru_cmd_par/dtc_rdo_mask_i_29" BEL "u_sru_cmd_par/dtc_rdo_mask_i_28" BEL "u_sru_cmd_par/dtc_rdo_mask_i_27" BEL "u_sru_cmd_par/dtc_rdo_mask_i_26" BEL "u_sru_cmd_par/dtc_rdo_mask_i_25" BEL "u_sru_cmd_par/dtc_rdo_mask_i_24" BEL "u_sru_cmd_par/dtc_rdo_mask_i_23" BEL "u_sru_cmd_par/dtc_rdo_mask_i_22" BEL "u_sru_cmd_par/dtc_rdo_mask_i_21" BEL "u_sru_cmd_par/dtc_rdo_mask_i_20" BEL "u_sru_cmd_par/dtc_rdo_mask_i_19" BEL "u_sru_cmd_par/dtc_rdo_mask_i_18" BEL "u_sru_cmd_par/dtc_rdo_mask_i_17" BEL "u_sru_cmd_par/dtc_rdo_mask_i_16" BEL "u_sru_cmd_par/dtc_rdo_mask_i_15" BEL "u_sru_cmd_par/dtc_rdo_mask_i_14" BEL "u_sru_cmd_par/dtc_rdo_mask_i_13" BEL "u_sru_cmd_par/dtc_rdo_mask_i_12" BEL "u_sru_cmd_par/dtc_rdo_mask_i_11" BEL "u_sru_cmd_par/dtc_rdo_mask_i_10" BEL "u_sru_cmd_par/dtc_rdo_mask_i_9" BEL "u_sru_cmd_par/dtc_rdo_mask_i_8" BEL "u_sru_cmd_par/dtc_rdo_mask_i_7" BEL "u_sru_cmd_par/dtc_rdo_mask_i_6" BEL "u_sru_cmd_par/dtc_rdo_mask_i_5" BEL "u_sru_cmd_par/dtc_rdo_mask_i_4" BEL "u_sru_cmd_par/dtc_rdo_mask_i_3" BEL "u_sru_cmd_par/dtc_rdo_mask_i_2" BEL "u_sru_cmd_par/dtc_rdo_mask_i_1" BEL "u_sru_cmd_par/dtc_rdo_mask_i_0" BEL "u_sru_cmd_par/rcmd_reply_dv" BEL "u_sru_cmd_par/rcmd_reply_data_31" BEL "u_sru_cmd_par/rcmd_reply_data_30" BEL "u_sru_cmd_par/rcmd_reply_data_29" BEL "u_sru_cmd_par/rcmd_reply_data_28" BEL "u_sru_cmd_par/rcmd_reply_data_27" BEL "u_sru_cmd_par/rcmd_reply_data_26" BEL "u_sru_cmd_par/rcmd_reply_data_25" BEL "u_sru_cmd_par/rcmd_reply_data_24" BEL "u_sru_cmd_par/rcmd_reply_data_23" BEL "u_sru_cmd_par/rcmd_reply_data_22" BEL "u_sru_cmd_par/rcmd_reply_data_21" BEL "u_sru_cmd_par/rcmd_reply_data_20" BEL "u_sru_cmd_par/rcmd_reply_data_19" BEL "u_sru_cmd_par/rcmd_reply_data_18" BEL "u_sru_cmd_par/rcmd_reply_data_17" BEL "u_sru_cmd_par/rcmd_reply_data_16" BEL "u_sru_cmd_par/rcmd_reply_data_15" BEL "u_sru_cmd_par/rcmd_reply_data_14" BEL "u_sru_cmd_par/rcmd_reply_data_13" BEL "u_sru_cmd_par/rcmd_reply_data_12" BEL "u_sru_cmd_par/rcmd_reply_data_11" BEL "u_sru_cmd_par/rcmd_reply_data_10" BEL "u_sru_cmd_par/rcmd_reply_data_9" BEL "u_sru_cmd_par/rcmd_reply_data_8" BEL "u_sru_cmd_par/rcmd_reply_data_7" BEL "u_sru_cmd_par/rcmd_reply_data_6" BEL "u_sru_cmd_par/rcmd_reply_data_5" BEL "u_sru_cmd_par/rcmd_reply_data_4" BEL "u_sru_cmd_par/rcmd_reply_data_3" BEL "u_sru_cmd_par/rcmd_reply_data_2" BEL "u_sru_cmd_par/rcmd_reply_data_1" BEL "u_sru_cmd_par/rcmd_reply_data_0" BEL "u_sru_cmd_par/spill_d" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_cmd_par/FastCmd_i" BEL "u_sru_cmd_par/test_pulse_en" BEL "htrig_d" BEL "spill_sync_d" BEL "sru_trig_synced_out_nim" BEL "u_sru_40dtc_top/DTCRamAllFlag_i" BEL "u_sru_cmd_par/reset_cmd" BEL "u_sru_trigger/tlu_event_number_15" BEL "u_sru_trigger/tlu_event_number_14" BEL "u_sru_trigger/tlu_event_number_13" BEL "u_sru_trigger/tlu_event_number_12" BEL "u_sru_trigger/tlu_event_number_11" BEL "u_sru_trigger/tlu_event_number_10" BEL "u_sru_trigger/tlu_event_number_9" BEL "u_sru_trigger/tlu_event_number_8" BEL "u_sru_trigger/tlu_event_number_7" BEL "u_sru_trigger/tlu_event_number_6" BEL "u_sru_trigger/tlu_event_number_5" BEL "u_sru_trigger/tlu_event_number_4" BEL "u_sru_trigger/tlu_event_number_3" BEL "u_sru_trigger/tlu_event_number_2" BEL "u_sru_trigger/tlu_event_number_1" BEL "u_sru_trigger/tlu_event_number_0" BEL "u_sru_trigger/tlu_event_number_shift_16" BEL "u_sru_trigger/tlu_event_number_shift_15" BEL "u_sru_trigger/tlu_event_number_shift_14" BEL "u_sru_trigger/tlu_event_number_shift_13" BEL "u_sru_trigger/tlu_event_number_shift_12" BEL "u_sru_trigger/tlu_event_number_shift_11" BEL "u_sru_trigger/tlu_event_number_shift_10" BEL "u_sru_trigger/tlu_event_number_shift_9" BEL "u_sru_trigger/tlu_event_number_shift_8" BEL "u_sru_trigger/tlu_event_number_shift_7" BEL "u_sru_trigger/tlu_event_number_shift_6" BEL "u_sru_trigger/tlu_event_number_shift_5" BEL "u_sru_trigger/tlu_event_number_shift_4" BEL "u_sru_trigger/tlu_event_number_shift_3" BEL "u_sru_trigger/tlu_event_number_shift_2" BEL "u_sru_trigger/tlu_event_number_shift_1" BEL "u_sru_trigger/tlu_event_number_shift_0" BEL "u_sru_trigger/u_ttc_decoder/st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/ttc_l1" BEL "u_sru_trigger/u_ttc_decoder/ttc_l0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_31" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_30" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_29" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_28" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_27" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_26" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_25" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_24" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_23" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_22" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_21" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_20" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_19" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_18" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_17" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_16" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_15" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_14" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_13" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2aMes8Cnt_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_st_FSM_FFd3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/st_FSM_FFd4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_23" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_22" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_21" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_20" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_19" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_18" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_17" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_16" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_15" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_14" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_13" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w2_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/cdh_w1_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word3_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word2_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_11" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_10" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_9" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_8" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_6" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_5" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_4" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_3" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2a_word1_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_12" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_7" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_2" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_1" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/L2_mes_strobe_0" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/ttc_l2r" BEL "u_sru_trigger/u_ttc_decoder/u_ttc_mgs_decode/ttc_l2aMesRdy" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_59" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_58" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_57" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_56" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_55" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_54" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_53" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_52" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_51" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_50" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_49" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_48" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_47" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_46" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_45" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_44" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_43" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_42" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_41" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_40" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_39" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_38" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_37" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_36" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_35" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_34" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_33" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_32" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_31" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_30" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_29" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_28" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_27" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_26" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_25" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_24" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_23" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_22" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_21" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_20" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_19" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_18" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_17" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_16" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_15" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_14" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_13" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_12" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_11" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_10" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_9" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_8" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_7" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_6" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_5" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_4" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_3" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_2" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_1" BEL "u_sru_trigger/u_trig_cnt/timestamp_i_0" BEL "u_sru_trigger/u_trig_cnt/event_cnt_29" BEL "u_sru_trigger/u_trig_cnt/event_cnt_28" BEL "u_sru_trigger/u_trig_cnt/event_cnt_27" BEL "u_sru_trigger/u_trig_cnt/event_cnt_26" BEL "u_sru_trigger/u_trig_cnt/event_cnt_25" BEL "u_sru_trigger/u_trig_cnt/event_cnt_24" BEL "u_sru_trigger/u_trig_cnt/event_cnt_23" BEL "u_sru_trigger/u_trig_cnt/event_cnt_22" BEL "u_sru_trigger/u_trig_cnt/event_cnt_21" BEL "u_sru_trigger/u_trig_cnt/event_cnt_20" BEL "u_sru_trigger/u_trig_cnt/event_cnt_19" BEL "u_sru_trigger/u_trig_cnt/event_cnt_18" BEL "u_sru_trigger/u_trig_cnt/event_cnt_17" BEL "u_sru_trigger/u_trig_cnt/event_cnt_16" BEL "u_sru_trigger/u_trig_cnt/event_cnt_15" BEL "u_sru_trigger/u_trig_cnt/event_cnt_14" BEL "u_sru_trigger/u_trig_cnt/event_cnt_13" BEL "u_sru_trigger/u_trig_cnt/event_cnt_12" BEL "u_sru_trigger/u_trig_cnt/event_cnt_11" BEL "u_sru_trigger/u_trig_cnt/event_cnt_10" BEL "u_sru_trigger/u_trig_cnt/event_cnt_9" BEL "u_sru_trigger/u_trig_cnt/event_cnt_8" BEL "u_sru_trigger/u_trig_cnt/event_cnt_7" BEL "u_sru_trigger/u_trig_cnt/event_cnt_6" BEL "u_sru_trigger/u_trig_cnt/event_cnt_5" BEL "u_sru_trigger/u_trig_cnt/event_cnt_4" BEL "u_sru_trigger/u_trig_cnt/event_cnt_3" BEL "u_sru_trigger/u_trig_cnt/event_cnt_2" BEL "u_sru_trigger/u_trig_cnt/event_cnt_1" BEL "u_sru_trigger/u_trig_cnt/event_cnt_0" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_31" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_30" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_29" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_28" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_27" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_26" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_25" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_24" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_23" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_22" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_21" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_20" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_19" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_18" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_17" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_16" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_15" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_14" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_13" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_12" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_11" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_10" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_9" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_8" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_7" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_6" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_5" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_4" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_3" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_2" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_1" BEL "u_sru_trigger/u_trig_cnt/abortcmd_cnt_0" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_31" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_30" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_29" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_28" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_27" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_26" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_25" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_24" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_23" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_22" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_21" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_20" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_19" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_18" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_17" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_16" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_15" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_14" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_13" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_12" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_11" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_10" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_9" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_8" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_7" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_6" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_5" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_4" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_3" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_2" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_1" BEL "u_sru_trigger/u_trig_cnt/rdocmd_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l1out_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l2a_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l0_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l2r_cnt_0" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_31" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_30" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_29" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_28" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_27" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_26" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_25" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_24" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_23" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_22" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_21" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_20" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_19" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_18" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_17" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_16" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_15" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_14" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_13" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_12" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_11" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_10" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_9" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_8" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_7" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_6" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_5" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_4" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_3" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_2" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_1" BEL "u_sru_trigger/u_trig_cnt/l1_cnt_0" BEL "u_sru_trigger/u_trig_cnt/event_countdown_31" BEL "u_sru_trigger/u_trig_cnt/event_countdown_30" BEL "u_sru_trigger/u_trig_cnt/event_countdown_29" BEL "u_sru_trigger/u_trig_cnt/event_countdown_28" BEL "u_sru_trigger/u_trig_cnt/event_countdown_27" BEL "u_sru_trigger/u_trig_cnt/event_countdown_26" BEL "u_sru_trigger/u_trig_cnt/event_countdown_25" BEL "u_sru_trigger/u_trig_cnt/event_countdown_24" BEL "u_sru_trigger/u_trig_cnt/event_countdown_23" BEL "u_sru_trigger/u_trig_cnt/event_countdown_22" BEL "u_sru_trigger/u_trig_cnt/event_countdown_21" BEL "u_sru_trigger/u_trig_cnt/event_countdown_20" BEL "u_sru_trigger/u_trig_cnt/event_countdown_19" BEL "u_sru_trigger/u_trig_cnt/event_countdown_18" BEL "u_sru_trigger/u_trig_cnt/event_countdown_17" BEL "u_sru_trigger/u_trig_cnt/event_countdown_16" BEL "u_sru_trigger/u_trig_cnt/event_countdown_15" BEL "u_sru_trigger/u_trig_cnt/event_countdown_14" BEL "u_sru_trigger/u_trig_cnt/event_countdown_13" BEL "u_sru_trigger/u_trig_cnt/event_countdown_12" BEL "u_sru_trigger/u_trig_cnt/event_countdown_11" BEL "u_sru_trigger/u_trig_cnt/event_countdown_10" BEL "u_sru_trigger/u_trig_cnt/event_countdown_9" BEL "u_sru_trigger/u_trig_cnt/event_countdown_8" BEL "u_sru_trigger/u_trig_cnt/event_countdown_7" BEL "u_sru_trigger/u_trig_cnt/event_countdown_6" BEL "u_sru_trigger/u_trig_cnt/event_countdown_5" BEL "u_sru_trigger/u_trig_cnt/event_countdown_4" BEL "u_sru_trigger/u_trig_cnt/event_countdown_3" BEL "u_sru_trigger/u_trig_cnt/event_countdown_2" BEL "u_sru_trigger/u_trig_cnt/event_countdown_1" BEL "u_sru_trigger/u_trig_cnt/event_countdown_0" BEL "u_sru_trigger/u_trig_cnt/clkcntb_3" BEL "u_sru_trigger/u_trig_cnt/clkcntb_2" BEL "u_sru_trigger/u_trig_cnt/clkcntb_1" BEL "u_sru_trigger/u_trig_cnt/clkcntb_0" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_ready_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_rdocmd_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_l1_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/prev_l0_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/timestamp_59" BEL "u_sru_trigger/u_trig_cnt/timestamp_58" BEL "u_sru_trigger/u_trig_cnt/timestamp_57" BEL "u_sru_trigger/u_trig_cnt/timestamp_56" BEL "u_sru_trigger/u_trig_cnt/timestamp_55" BEL "u_sru_trigger/u_trig_cnt/timestamp_54" BEL "u_sru_trigger/u_trig_cnt/timestamp_53" BEL "u_sru_trigger/u_trig_cnt/timestamp_52" BEL "u_sru_trigger/u_trig_cnt/timestamp_51" BEL "u_sru_trigger/u_trig_cnt/timestamp_50" BEL "u_sru_trigger/u_trig_cnt/timestamp_49" BEL "u_sru_trigger/u_trig_cnt/timestamp_48" BEL "u_sru_trigger/u_trig_cnt/timestamp_47" BEL "u_sru_trigger/u_trig_cnt/timestamp_46" BEL "u_sru_trigger/u_trig_cnt/timestamp_45" BEL "u_sru_trigger/u_trig_cnt/timestamp_44" BEL "u_sru_trigger/u_trig_cnt/timestamp_43" BEL "u_sru_trigger/u_trig_cnt/timestamp_42" BEL "u_sru_trigger/u_trig_cnt/timestamp_41" BEL "u_sru_trigger/u_trig_cnt/timestamp_40" BEL "u_sru_trigger/u_trig_cnt/timestamp_39" BEL "u_sru_trigger/u_trig_cnt/timestamp_38" BEL "u_sru_trigger/u_trig_cnt/timestamp_37" BEL "u_sru_trigger/u_trig_cnt/timestamp_36" BEL "u_sru_trigger/u_trig_cnt/timestamp_35" BEL "u_sru_trigger/u_trig_cnt/timestamp_34" BEL "u_sru_trigger/u_trig_cnt/timestamp_33" BEL "u_sru_trigger/u_trig_cnt/timestamp_32" BEL "u_sru_trigger/u_trig_cnt/timestamp_31" BEL "u_sru_trigger/u_trig_cnt/timestamp_30" BEL "u_sru_trigger/u_trig_cnt/timestamp_29" BEL "u_sru_trigger/u_trig_cnt/timestamp_28" BEL "u_sru_trigger/u_trig_cnt/timestamp_27" BEL "u_sru_trigger/u_trig_cnt/timestamp_26" BEL "u_sru_trigger/u_trig_cnt/timestamp_25" BEL "u_sru_trigger/u_trig_cnt/timestamp_24" BEL "u_sru_trigger/u_trig_cnt/timestamp_23" BEL "u_sru_trigger/u_trig_cnt/timestamp_22" BEL "u_sru_trigger/u_trig_cnt/timestamp_21" BEL "u_sru_trigger/u_trig_cnt/timestamp_20" BEL "u_sru_trigger/u_trig_cnt/timestamp_19" BEL "u_sru_trigger/u_trig_cnt/timestamp_18" BEL "u_sru_trigger/u_trig_cnt/timestamp_17" BEL "u_sru_trigger/u_trig_cnt/timestamp_16" BEL "u_sru_trigger/u_trig_cnt/timestamp_15" BEL "u_sru_trigger/u_trig_cnt/timestamp_14" BEL "u_sru_trigger/u_trig_cnt/timestamp_13" BEL "u_sru_trigger/u_trig_cnt/timestamp_12" BEL "u_sru_trigger/u_trig_cnt/timestamp_11" BEL "u_sru_trigger/u_trig_cnt/timestamp_10" BEL "u_sru_trigger/u_trig_cnt/timestamp_9" BEL "u_sru_trigger/u_trig_cnt/timestamp_8" BEL "u_sru_trigger/u_trig_cnt/timestamp_7" BEL "u_sru_trigger/u_trig_cnt/timestamp_6" BEL "u_sru_trigger/u_trig_cnt/timestamp_5" BEL "u_sru_trigger/u_trig_cnt/timestamp_4" BEL "u_sru_trigger/u_trig_cnt/timestamp_3" BEL "u_sru_trigger/u_trig_cnt/timestamp_2" BEL "u_sru_trigger/u_trig_cnt/timestamp_1" BEL "u_sru_trigger/u_trig_cnt/timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_ready_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_rdocmd_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_l0_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_31" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_30" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_29" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_28" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_27" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_26" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_25" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_24" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_23" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_22" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_21" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_20" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_19" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_18" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_17" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_16" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_15" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_14" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_13" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_12" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_11" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_10" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_9" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_8" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_7" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_6" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_5" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_4" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_3" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_2" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_1" BEL "u_sru_trigger/u_trig_cnt/last_l1_timestamp_0" BEL "u_sru_trigger/u_trig_cnt/abortcmd" BEL "u_sru_trigger/u_trig_cnt/rdocmd" BEL "u_sru_trigger/u_trig_cnt/event_cnt_wr_en" BEL "u_sru_trigger/u_trig_cnt/stc" BEL "u_sru_trigger/u_trig_cnt/stb" BEL "u_sru_trigger/u_trig_cnt/stall_events" BEL "u_sru_trigger/u_trig_cnt/BusyFlag_d" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd4" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_15" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_14" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_13" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_12" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_11" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_10" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_9" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_8" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_7" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_6" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_5" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_4" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_3" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_2" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_1" BEL "u_sru_trigger/u_test_trig_gen/clkcnta_0" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd1" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd2" BEL "u_sru_trigger/u_test_trig_gen/st_FSM_FFd3" BEL "u_sru_trigger/u_test_trig_gen/sta_FSM_FFd1" BEL "u_sru_trigger/u_test_trig_gen/sta_FSM_FFd2" BEL "u_sru_trigger/u_test_trig_gen/test_trig" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_15" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_14" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_13" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_12" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_11" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_10" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_9" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_8" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_7" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_6" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_5" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_4" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_3" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_2" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_1" BEL "u_sru_trigger/u_test_trig_gen/clkcnt_0" BEL "u_sru_trigger/u_test_trig_gen/test_l0" BEL "u_sru_trigger/u_test_trig_gen/test_l2a" BEL "u_sru_trigger/u_test_trig_gen/test_l1" BEL "u_sru_trigger/u_test_trig_gen/l0_trig" BEL "u_sru_trigger/u_test_trig_gen/test_pulse" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd3" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_11" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_10" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_9" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_8" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_7" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_6" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_5" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_4" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_3" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_2" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_1" BEL "u_sru_trigger/u_trig_err_detect/trigerr_cnt_i_0" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd1" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd4" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd2" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd6" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd7" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd5" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd8" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd9" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd10" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd11" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd13" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd14" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd12" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd16" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd17" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd15" BEL "u_sru_trigger/u_trig_err_detect/st_FSM_FFd18" BEL "u_sru_trigger/u_trig_err_detect/DtcRamClr" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_20" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_19" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_18" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_17" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_16" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_15" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_13" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_11" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_9" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_8" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_7" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_6" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_5" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_4" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_3" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_2" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_1" BEL "u_sru_trigger/u_trig_err_detect/DebugReg_0" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_15" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_14" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_13" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_12" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_11" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_10" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_9" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_8" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_7" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_6" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_5" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_4" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_3" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_2" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_1" BEL "u_sru_trigger/u_trig_err_detect/clkcnt_0" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_5" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_2" BEL "u_sru_trigger/u_trig_err_detect/trigerr_i_1" BEL "u_sru_trigger/u_trig_err_detect/abortcmd_c" BEL "u_sru_trigger/u_trig_err_detect/rdocmd_c" BEL "u_sru_trigger/u_trig_err_detect/trig_busy" BEL "u_sru_trigger/u_trig_err_detect/ddl_tx_start_i" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/clkcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_dv" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_data_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/fifo_rd_en" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/psscan_flag_d" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/WordAlignFlag_d" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_cmd_par/synch_dcs/o" BEL "u_sru_cmd_par/synch_dcs/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_40/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_40/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_40/Mshreg_o" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/ODDR_DTCOUT_pins<1>" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_dtc_dout_ser/pdata_reg_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/last_packet_sync_ff_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/Mshreg_last_packet_sync_ff_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_d_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_dd_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_d_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_dd_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_d" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdo_cnt_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_39" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_38" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_37" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_36" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_35" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_34" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_33" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_32" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_31" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_30" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_29" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_28" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_27" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_26" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_25" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_24" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_23" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_22" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_21" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_20" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_19" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_18" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_17" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_16" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_15" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_14" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_13" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_12" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_11" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_10" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_9" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_8" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/rdocmd_i_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/last_packet_sync_ff_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_1_changed_0" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_7" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_6" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_5" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_4" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_3" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_2" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_1" BEL "u_sru_40dtc_top/u_dtc_chrdo_fsm/index_0_changed_0" BEL "u_main_clk_gen/TrigIOClkSel" BEL "u_SCLKPhaseDetect/cnt_i_1" BEL "u_SCLKPhaseDetect/cnt_i_0" BEL "u_SCLKPhaseDetect/st_FSM_FFd1" BEL "u_SCLKPhaseDetect/st_FSM_FFd2" BEL "u_SCLKPhaseDetect/sclkphasecnt_1" BEL "u_SCLKPhaseDetect/sclkphasecnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/clkcnt_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/st_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_data_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/fifo_rd_en" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_dv" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_31" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_30" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_29" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_28" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_27" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_26" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_25" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_24" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_23" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_22" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_21" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_20" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_19" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_18" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_17" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_16" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_15" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_14" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_13" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_12" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/udp_cmd_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_15" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_14" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_13" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_12" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_11" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_10" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_9" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_8" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_7" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_6" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_5" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_4" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_3" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_2" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_1" BEL "u_sru_cmd_par/u_dtcout/dtc_deser_dout_0" BEL "u_sru_cmd_par/u_ResetSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_ResetSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_ResetSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_ResetSwitch/pulse_out_i" BEL "u_sru_cmd_par/u_BusyClrSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_BusyClrSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_BusyClrSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_BusyClrSwitch/pulse_out_i" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/st_FSM_FFd1" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/st_FSM_FFd2" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_23" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_22" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_21" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_20" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_19" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_18" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_17" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_16" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_15" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_14" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_13" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_12" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_11" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_10" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_9" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_8" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_7" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_6" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_5" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_4" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_3" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_2" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_1" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/cnt_i_0" BEL "u_sru_cmd_par/u_FPGAReLoadSwitch/pulse_out_i" BEL "u_sru_cmd_par/usrudcsreplyack/st_FSM_FFd1" BEL "u_sru_cmd_par/usrudcsreplyack/st_FSM_FFd2" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_update" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_63" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_62" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_61" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_60" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_59" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_58" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_57" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_56" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_55" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_54" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_53" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_52" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_51" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_50" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_49" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_48" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_47" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_46" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_45" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_44" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_43" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_42" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_41" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_40" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_39" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_38" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_37" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_36" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_35" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_34" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_33" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_32" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_31" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_30" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_29" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_28" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_27" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_26" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_25" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_24" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_23" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_22" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_21" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_20" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_19" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_18" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_17" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_16" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_15" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_14" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_13" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_12" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_11" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_10" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_9" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_8" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_7" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_6" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_5" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_4" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_3" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_2" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_1" BEL "u_sru_cmd_par/usrudcsreplyack/dcs_cmd_reply_0" PIN "u_sru_cmd_par/u_srutempmonitor/SYSMON_INST_pins<10>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<65>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout4_buf"; PIN BUFR_SC_pins<2> = BEL "BUFR_SC" PINNAME I; PIN u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_main_clk_gen/UTLUSyncPLL/mmcm_adv_inst_pins<2> = BEL "u_main_clk_gen/UTLUSyncPLL/mmcm_adv_inst" PINNAME CLKIN1; PIN u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<2> = BEL "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst" PINNAME CLKIN1; PIN u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<37> = BEL "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst" PINNAME PSCLK; TIMEGRP clk_40m = BEL "clkdiv_0" BEL "clkdiv_1" BEL "clkdiv_2" BEL "clkdiv_3" BEL "clkdiv_4" BEL "clkdiv_5" BEL "clkdiv_6" BEL "clkdiv_7" BEL "clkdiv_8" BEL "clkdiv_9" BEL "clkdiv_10" BEL "clkdiv_11" BEL "clkdiv_12" BEL "clkdiv_13" BEL "clkdiv_14" BEL "clkdiv_15" BEL "clkdiv_16" BEL "clkdiv_17" BEL "clkdiv_18" BEL "clkdiv_19" BEL "clkdiv_20" BEL "clkdiv_21" BEL "clkdiv_22" BEL "clkdiv_23" BEL "clkdiv_24" BEL "clkdiv_25" PIN "BUFR_SC_pins<2>" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_FlashToUDP/u_UDPSCConv/synch_wr/o" BEL "u_FlashToUDP/u_UDPSCConv/synch_wr/Mshreg_o" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd2" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd3" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd1" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd4" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd5" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd6" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd7" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd9" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd10" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd8" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd11" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psen" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psscan_flag" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_15" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_14" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_13" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_12" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_11" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_10" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_9" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_8" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_7" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_6" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_5" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_4" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_3" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_2" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_1" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_0" BEL "u_ResetSwitch/st_FSM_FFd1" BEL "u_ResetSwitch/st_FSM_FFd2" BEL "u_ResetSwitch/cnt_i_23" BEL "u_ResetSwitch/cnt_i_22" BEL "u_ResetSwitch/cnt_i_21" BEL "u_ResetSwitch/cnt_i_20" BEL "u_ResetSwitch/cnt_i_19" BEL "u_ResetSwitch/cnt_i_18" BEL "u_ResetSwitch/cnt_i_17" BEL "u_ResetSwitch/cnt_i_16" BEL "u_ResetSwitch/cnt_i_15" BEL "u_ResetSwitch/cnt_i_14" BEL "u_ResetSwitch/cnt_i_13" BEL "u_ResetSwitch/cnt_i_12" BEL "u_ResetSwitch/cnt_i_11" BEL "u_ResetSwitch/cnt_i_10" BEL "u_ResetSwitch/cnt_i_9" BEL "u_ResetSwitch/cnt_i_8" BEL "u_ResetSwitch/cnt_i_7" BEL "u_ResetSwitch/cnt_i_6" BEL "u_ResetSwitch/cnt_i_5" BEL "u_ResetSwitch/cnt_i_4" BEL "u_ResetSwitch/cnt_i_3" BEL "u_ResetSwitch/cnt_i_2" BEL "u_ResetSwitch/cnt_i_1" BEL "u_ResetSwitch/cnt_i_0" BEL "u_ResetSwitch/pulse_out_i" PIN "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_main_clk_gen/UTLUSyncPLL/mmcm_adv_inst_pins<2>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<2>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<37>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<2>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<37>"; TIMEGRP u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout0 = BEL "clkdiv_0" BEL "clkdiv_1" BEL "clkdiv_2" BEL "clkdiv_3" BEL "clkdiv_4" BEL "clkdiv_5" BEL "clkdiv_6" BEL "clkdiv_7" BEL "clkdiv_8" BEL "clkdiv_9" BEL "clkdiv_10" BEL "clkdiv_11" BEL "clkdiv_12" BEL "clkdiv_13" BEL "clkdiv_14" BEL "clkdiv_15" BEL "clkdiv_16" BEL "clkdiv_17" BEL "clkdiv_18" BEL "clkdiv_19" BEL "clkdiv_20" BEL "clkdiv_21" BEL "clkdiv_22" BEL "clkdiv_23" BEL "clkdiv_24" BEL "clkdiv_25" PIN "BUFR_SC_pins<2>" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_FlashToUDP/u_UDPSCConv/synch_wr/o" BEL "u_FlashToUDP/u_UDPSCConv/synch_wr/Mshreg_o" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd2" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd3" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd1" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd4" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd5" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd6" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd7" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd9" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd10" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd8" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd11" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psen" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psscan_flag" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_15" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_14" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_13" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_12" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_11" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_10" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_9" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_8" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_7" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_6" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_5" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_4" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_3" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_2" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_1" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_0" BEL "u_main_clk_gen/USGclkMux/u_brdclk_pll/clkout1_buf" BEL "u_ResetSwitch/st_FSM_FFd1" BEL "u_ResetSwitch/st_FSM_FFd2" BEL "u_ResetSwitch/cnt_i_23" BEL "u_ResetSwitch/cnt_i_22" BEL "u_ResetSwitch/cnt_i_21" BEL "u_ResetSwitch/cnt_i_20" BEL "u_ResetSwitch/cnt_i_19" BEL "u_ResetSwitch/cnt_i_18" BEL "u_ResetSwitch/cnt_i_17" BEL "u_ResetSwitch/cnt_i_16" BEL "u_ResetSwitch/cnt_i_15" BEL "u_ResetSwitch/cnt_i_14" BEL "u_ResetSwitch/cnt_i_13" BEL "u_ResetSwitch/cnt_i_12" BEL "u_ResetSwitch/cnt_i_11" BEL "u_ResetSwitch/cnt_i_10" BEL "u_ResetSwitch/cnt_i_9" BEL "u_ResetSwitch/cnt_i_8" BEL "u_ResetSwitch/cnt_i_7" BEL "u_ResetSwitch/cnt_i_6" BEL "u_ResetSwitch/cnt_i_5" BEL "u_ResetSwitch/cnt_i_4" BEL "u_ResetSwitch/cnt_i_3" BEL "u_ResetSwitch/cnt_i_2" BEL "u_ResetSwitch/cnt_i_1" BEL "u_ResetSwitch/cnt_i_0" BEL "u_ResetSwitch/pulse_out_i" PIN "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<2>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<37>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<2>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<37>"; TIMEGRP u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout0_0 = BEL "clkdiv_0" BEL "clkdiv_1" BEL "clkdiv_2" BEL "clkdiv_3" BEL "clkdiv_4" BEL "clkdiv_5" BEL "clkdiv_6" BEL "clkdiv_7" BEL "clkdiv_8" BEL "clkdiv_9" BEL "clkdiv_10" BEL "clkdiv_11" BEL "clkdiv_12" BEL "clkdiv_13" BEL "clkdiv_14" BEL "clkdiv_15" BEL "clkdiv_16" BEL "clkdiv_17" BEL "clkdiv_18" BEL "clkdiv_19" BEL "clkdiv_20" BEL "clkdiv_21" BEL "clkdiv_22" BEL "clkdiv_23" BEL "clkdiv_24" BEL "clkdiv_25" PIN "BUFR_SC_pins<2>" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_FlashToUDP/u_UDPSCConv/synch_wr/o" BEL "u_FlashToUDP/u_UDPSCConv/synch_wr/Mshreg_o" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd2" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd3" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd1" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd4" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd5" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd6" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd7" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd9" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd10" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd8" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/st_FSM_FFd11" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psen" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psscan_flag" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_15" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_14" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_13" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_12" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_11" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_10" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_9" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_8" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_7" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_6" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_5" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_4" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_3" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_2" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_1" BEL "u_main_clk_gen/USerClkSrc/u_psctrl/psstepcnt_0" BEL "u_main_clk_gen/USGclkMux/u_brdclk_pll/clkout1_buf" BEL "u_ResetSwitch/st_FSM_FFd1" BEL "u_ResetSwitch/st_FSM_FFd2" BEL "u_ResetSwitch/cnt_i_23" BEL "u_ResetSwitch/cnt_i_22" BEL "u_ResetSwitch/cnt_i_21" BEL "u_ResetSwitch/cnt_i_20" BEL "u_ResetSwitch/cnt_i_19" BEL "u_ResetSwitch/cnt_i_18" BEL "u_ResetSwitch/cnt_i_17" BEL "u_ResetSwitch/cnt_i_16" BEL "u_ResetSwitch/cnt_i_15" BEL "u_ResetSwitch/cnt_i_14" BEL "u_ResetSwitch/cnt_i_13" BEL "u_ResetSwitch/cnt_i_12" BEL "u_ResetSwitch/cnt_i_11" BEL "u_ResetSwitch/cnt_i_10" BEL "u_ResetSwitch/cnt_i_9" BEL "u_ResetSwitch/cnt_i_8" BEL "u_ResetSwitch/cnt_i_7" BEL "u_ResetSwitch/cnt_i_6" BEL "u_ResetSwitch/cnt_i_5" BEL "u_ResetSwitch/cnt_i_4" BEL "u_ResetSwitch/cnt_i_3" BEL "u_ResetSwitch/cnt_i_2" BEL "u_ResetSwitch/cnt_i_1" BEL "u_ResetSwitch/cnt_i_0" BEL "u_ResetSwitch/pulse_out_i" PIN "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<2>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<37>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<2>" PIN "u_main_clk_gen/USerClkSrc/USerClkGen/mmcm_adv_inst_pins<37>"; PIN u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; TIMEGRP clk10m_i = BEL "BUFG_SC" BEL "u_FlashToUDP/u_scController/scRXqueue/rd_eof_i" BEL "u_FlashToUDP/u_scController/scRXqueue/rd_sof_i" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_8" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_7" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_6" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_5" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_4" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_3" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_2" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_1" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pf_empty_q" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grhf.rhf/ram_valid_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/frame_port_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/frame_port_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_63" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_62" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_61" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_60" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_59" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_58" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_57" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_56" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_55" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_54" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_53" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_52" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_51" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_50" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_49" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_48" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_47" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_46" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_45" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_44" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_43" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_42" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_41" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_40" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_39" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_38" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_37" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_36" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_35" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_34" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_33" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_32" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_31" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_30" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_29" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_28" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_27" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_26" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_25" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_24" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_23" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_22" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_21" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_20" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_19" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_18" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_17" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_16" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_15" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_14" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_13" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/pf_wr_en" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrb_q" BEL "u_FlashToUDP/u_scController/scRplyQueue/sc_ack_q" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrd" BEL "u_FlashToUDP/u_scController/scRplyQueue/sc_frame_q" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_counter_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/eof_flag" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/state_FSM_FFd1" BEL "u_FlashToUDP/u_scController/scRXdecode2/state_FSM_FFd3" BEL "u_FlashToUDP/u_scController/scRXdecode2/state_FSM_FFd2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_error_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_error_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_error_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_126" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_125" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_124" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_123" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_122" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_121" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_120" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_119" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_118" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_117" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_116" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_115" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_114" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_113" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_112" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_111" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_110" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_109" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_108" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_107" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_106" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_105" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_104" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_103" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_102" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_101" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_100" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_99" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_98" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_97" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_96" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_95" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_94" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_93" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_92" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_91" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_90" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_89" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_88" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_87" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_86" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_85" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_84" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_83" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_82" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_81" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_80" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_79" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_78" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_77" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_76" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_75" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_74" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_73" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_72" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_71" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_70" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_69" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_68" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_67" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_66" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_65" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_64" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_63" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_62" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_61" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_60" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_59" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_58" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_57" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_56" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_55" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_54" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_53" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_52" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_51" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_50" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_49" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_48" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_47" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_46" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_45" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_44" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_43" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_42" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_41" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_40" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_39" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_38" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_37" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_36" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_35" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_34" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_33" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_32" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_30" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_29" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_28" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_27" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_26" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_25" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_24" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_frame" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_wr" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_30" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_29" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_28" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_27" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_26" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_25" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_24" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_op_i" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_length_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_IP_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_IP_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/error_flag" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_30" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_29" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_28" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_27" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_26" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_25" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_24" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_0" BEL "u_FlashToUDP/u_FlashTop/synch_reset/o" BEL "u_FlashToUDP/u_FlashTop/synch_reset/Mshreg_o" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_16_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_16_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_17_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_17_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_18_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_18_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_19_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_19_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_21_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_21_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_22_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_22_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_20_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_20_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_23_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_23_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_24_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_24_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_25_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_25_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_26_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_26_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_27_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_27_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_28_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_28_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_29_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_29_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_30_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_30_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_0_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_1_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_2_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_4_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_5_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_3_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_6_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_7_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_8_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_9_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_10_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_11_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_12_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_13_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_14_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_15_BRB2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_15_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_15_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_31" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_30" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_29" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_28" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_27" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_26" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_25" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_24" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_23" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_22" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_21" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_20" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_19" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_18" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_17" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_16" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_15" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_14" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_13" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_12" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_11" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_10" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_9" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_8" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_7" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_6" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_5" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_en" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_op" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_addr_0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_26" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_25" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_24" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_23" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_22" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_21" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_20" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_19" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_18" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_17" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_16" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_15" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_14" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_13" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_12" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_11" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_10" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_9" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_8" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_7" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_6" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_5" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_ack" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQ_T" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/FLASH_WE_B" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/FLASH_CS_B" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/FLASH_OE_B_i" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_23" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_22" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_21" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_20" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_19" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_18" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_17" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_16" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_16" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_31" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_30" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_29" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_28" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_27" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_26" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_25" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_24" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_23" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_22" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_21" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_20" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_19" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_18" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_17" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_16" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMD" PIN "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>"; TIMEGRP clk10m_i_0 = BEL "BUFG_SC" BEL "u_FlashToUDP/u_scController/scRXqueue/rd_eof_i" BEL "u_FlashToUDP/u_scController/scRXqueue/rd_sof_i" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_8" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_7" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_6" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_5" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_4" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_3" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_2" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_1" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pf_empty_q" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grhf.rhf/ram_valid_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/frame_port_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/frame_port_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_63" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_62" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_61" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_60" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_59" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_58" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_57" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_56" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_55" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_54" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_53" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_52" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_51" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_50" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_49" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_48" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_47" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_46" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_45" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_44" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_43" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_42" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_41" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_40" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_39" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_38" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_37" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_36" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_35" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_34" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_33" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_32" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_31" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_30" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_29" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_28" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_27" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_26" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_25" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_24" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_23" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_22" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_21" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_20" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_19" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_18" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_17" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_16" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_15" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_14" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_13" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/pf_wr_en" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrb_q" BEL "u_FlashToUDP/u_scController/scRplyQueue/sc_ack_q" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrd" BEL "u_FlashToUDP/u_scController/scRplyQueue/sc_frame_q" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_counter_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/eof_flag" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/state_FSM_FFd1" BEL "u_FlashToUDP/u_scController/scRXdecode2/state_FSM_FFd3" BEL "u_FlashToUDP/u_scController/scRXdecode2/state_FSM_FFd2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_error_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_error_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_error_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_126" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_125" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_124" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_123" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_122" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_121" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_120" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_119" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_118" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_117" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_116" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_115" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_114" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_113" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_112" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_111" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_110" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_109" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_108" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_107" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_106" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_105" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_104" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_103" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_102" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_101" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_100" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_99" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_98" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_97" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_96" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_95" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_94" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_93" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_92" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_91" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_90" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_89" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_88" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_87" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_86" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_85" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_84" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_83" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_82" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_81" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_80" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_79" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_78" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_77" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_76" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_75" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_74" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_73" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_72" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_71" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_70" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_69" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_68" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_67" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_66" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_65" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_64" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_63" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_62" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_61" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_60" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_59" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_58" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_57" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_56" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_55" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_54" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_53" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_52" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_51" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_50" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_49" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_48" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_47" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_46" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_45" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_44" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_43" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_42" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_41" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_40" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_39" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_38" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_37" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_36" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_35" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_34" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_33" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_32" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_30" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_29" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_28" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_27" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_26" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_25" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_24" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_frame" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_wr" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_30" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_29" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_28" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_27" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_26" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_25" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_24" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_op_i" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_length_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_IP_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_IP_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/error_flag" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_30" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_29" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_28" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_27" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_26" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_25" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_24" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_0" BEL "u_FlashToUDP/u_FlashTop/synch_reset/o" BEL "u_FlashToUDP/u_FlashTop/synch_reset/Mshreg_o" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_16_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_16_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_17_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_17_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_18_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_18_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_19_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_19_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_21_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_21_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_22_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_22_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_20_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_20_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_23_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_23_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_24_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_24_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_25_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_25_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_26_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_26_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_27_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_27_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_28_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_28_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_29_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_29_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_30_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_30_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_0_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_1_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_2_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_4_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_5_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_3_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_6_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_7_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_8_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_9_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_10_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_11_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_12_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_13_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_14_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_15_BRB2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_15_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_15_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_31" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_30" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_29" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_28" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_27" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_26" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_25" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_24" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_23" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_22" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_21" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_20" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_19" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_18" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_17" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_16" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_15" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_14" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_13" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_12" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_11" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_10" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_9" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_8" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_7" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_6" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_5" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_en" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_op" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_addr_0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_26" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_25" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_24" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_23" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_22" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_21" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_20" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_19" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_18" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_17" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_16" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_15" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_14" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_13" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_12" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_11" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_10" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_9" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_8" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_7" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_6" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_5" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_ack" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQ_T" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/FLASH_WE_B" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/FLASH_CS_B" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/FLASH_OE_B_i" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_23" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_22" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_21" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_20" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_19" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_18" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_17" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_16" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_16" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_31" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_30" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_29" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_28" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_27" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_26" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_25" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_24" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_23" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_22" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_21" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_20" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_19" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_18" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_17" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_16" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMD" PIN "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>"; TIMEGRP clk10m_i_1 = BEL "BUFG_SC" BEL "u_FlashToUDP/u_scController/scRXqueue/rd_eof_i" BEL "u_FlashToUDP/u_scController/scRXqueue/rd_sof_i" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_8" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_7" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_6" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_5" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_4" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_3" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_2" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_1" BEL "u_FlashToUDP/u_scController/scRXqueue/rdcounter_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pf_empty_q" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grhf.rhf/ram_valid_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrcounter_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/frame_port_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/frame_port_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_63" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_62" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_61" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_60" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_59" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_58" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_57" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_56" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_55" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_54" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_53" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_52" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_51" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_50" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_49" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_48" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_47" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_46" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_45" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_44" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_43" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_42" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_41" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_40" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_39" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_38" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_37" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_36" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_35" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_34" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_33" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_32" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_31" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_30" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_29" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_28" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_27" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_26" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_25" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_24" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_23" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_22" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_21" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_20" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_19" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_18" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_17" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_16" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_15" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_14" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_13" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrdata_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/pf_wr_en" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrb_q" BEL "u_FlashToUDP/u_scController/scRplyQueue/sc_ack_q" BEL "u_FlashToUDP/u_scController/scRplyQueue/wrd" BEL "u_FlashToUDP/u_scController/scRplyQueue/sc_frame_q" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_counter_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/eof_flag" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmdinfo_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/state_FSM_FFd1" BEL "u_FlashToUDP/u_scController/scRXdecode2/state_FSM_FFd3" BEL "u_FlashToUDP/u_scController/scRXdecode2/state_FSM_FFd2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_error_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_error_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_error_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_126" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_125" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_124" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_123" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_122" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_121" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_120" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_119" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_118" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_117" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_116" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_115" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_114" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_113" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_112" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_111" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_110" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_109" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_108" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_107" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_106" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_105" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_104" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_103" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_102" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_101" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_100" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_99" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_98" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_97" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_96" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_95" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_94" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_93" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_92" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_91" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_90" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_89" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_88" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_87" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_86" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_85" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_84" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_83" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_82" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_81" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_80" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_79" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_78" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_77" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_76" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_75" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_74" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_73" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_72" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_71" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_70" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_69" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_68" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_67" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_66" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_65" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_64" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_63" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_62" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_61" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_60" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_59" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_58" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_57" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_56" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_55" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_54" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_53" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_52" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_51" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_50" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_49" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_48" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_47" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_46" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_45" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_44" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_43" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_42" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_41" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_40" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_39" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_38" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_37" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_36" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_35" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_34" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_33" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_32" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_30" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_29" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_28" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_27" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_26" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_25" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_24" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_rply_bulk_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_frame" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_wr" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_30" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_29" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_28" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_27" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_26" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_25" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_24" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_data_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_addr_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/sc_op_i" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_length_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_port_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_IP_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_IP_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/error_flag" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_30" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_29" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_28" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_27" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_26" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_25" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_24" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_cmd_0" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_31" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_23" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_22" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_21" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_20" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_19" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_18" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_17" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_16" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_15" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_14" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_13" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_12" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_11" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_10" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_9" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_8" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_7" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_6" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_5" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_4" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_3" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_2" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_1" BEL "u_FlashToUDP/u_scController/scRXdecode2/frame_subaddress_0" BEL "u_FlashToUDP/u_FlashTop/synch_reset/o" BEL "u_FlashToUDP/u_FlashTop/synch_reset/Mshreg_o" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_16_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_16_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_17_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_17_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_18_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_18_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_19_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_19_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_21_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_21_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_22_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_22_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_20_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_20_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_23_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_23_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_24_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_24_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_25_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_25_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_26_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_26_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_27_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_27_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_28_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_28_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_29_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_29_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_30_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_30_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_31_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_0_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_1_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_2_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_4_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_5_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_3_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_6_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_7_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_8_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_9_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_10_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_11_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_12_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_13_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_14_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_15_BRB2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_15_BRB1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_i_15_BRB0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/st_FSM_FFd4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_31" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_30" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_29" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_28" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_27" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_26" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_25" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_24" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_23" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_22" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_21" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_20" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_19" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_18" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_17" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_16" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_15" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_14" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_13" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_12" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_11" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_10" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_9" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_8" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_7" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_6" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_5" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/local_ip_0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_en" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_op" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_addr_0" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_26" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_25" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_24" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_23" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_22" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_21" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_20" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_19" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_18" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_17" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_16" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_15" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_14" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_13" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_12" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_11" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_10" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_9" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_8" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_7" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_6" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_5" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_4" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_3" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_2" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_1" BEL "u_FlashToUDP/u_FlashTop/u_ReadIPinFlash/ip_sc_cnt_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_ack" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQ_T" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/FLASH_WE_B" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/FLASH_CS_B" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/FLASH_OE_B_i" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/state_FSM_FFd5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/wpcount_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/DQout_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_23" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_22" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_21" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_20" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_19" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_18" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_17" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_16" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/A_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_16" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_error_0" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_31" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_30" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_29" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_28" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_27" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_26" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_25" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_24" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_23" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_22" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_21" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_20" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_19" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_18" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_17" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_16" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_15" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_14" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_13" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_12" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_11" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_10" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_9" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_8" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_7" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_6" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_5" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_4" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_3" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_2" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_1" BEL "u_FlashToUDP/u_FlashTop/u_sc_flash_if/sc_rply_data_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMC" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD_D1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM65_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM66_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM67_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM68_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM69_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM70_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM71_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM72_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM73_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM74_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM75_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM76_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM77_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM78_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM79_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM80_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMD" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMA" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMB" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMC" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMD" PIN "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>"; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKDIV; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKDIV; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout1 = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_a/o" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_a/Mshreg_o" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/wren" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/wren" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout2_buf" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout1_0 = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_a/o" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_a/Mshreg_o" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/wren" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/wren" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout2_buf" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout1_1 = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_a/o" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_a/Mshreg_o" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/wren" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/wren" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout2_buf" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout1_2 = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_a/o" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_a/Mshreg_o" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/wren" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/wren" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout2_buf" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout1_3 = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/cnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_good_frame" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_wr_enable" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_175" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_174" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_173" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_172" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_171" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_170" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_169" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_168" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_167" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_166" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_165" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_164" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_163" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_162" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_161" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_160" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_159" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_158" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_157" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_156" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_155" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_154" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_153" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_152" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_151" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_150" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_149" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_148" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_147" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_146" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_145" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_144" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_143" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_142" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_141" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_140" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_139" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_138" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_137" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_136" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_135" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_134" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_133" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_132" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_131" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_130" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_129" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_128" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_127" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_126" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_125" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_124" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_123" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_122" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_121" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_120" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_119" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_118" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_117" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_116" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_115" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_114" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_113" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_112" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_111" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_110" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_109" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_108" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_107" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_106" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_105" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_104" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_103" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_102" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_101" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_100" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_99" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_98" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_97" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_96" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_95" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_94" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_93" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_92" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_91" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_90" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_89" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_88" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_87" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_86" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_85" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_84" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_83" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_82" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_81" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_80" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_79" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_78" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_77" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_76" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_75" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_74" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_73" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_72" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_71" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_70" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_69" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_68" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_67" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_66" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_65" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_64" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_63" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_62" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_61" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_60" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_59" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_58" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_57" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_56" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_55" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_54" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_53" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_52" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_51" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_50" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_49" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_48" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_47" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_46" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_45" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_44" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_43" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_42" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_41" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_40" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_39" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_38" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_37" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_36" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_35" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_34" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_33" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_32" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_udp_frame_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/dcs_rx_data_valid" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_wr/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/synch_bitclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/detcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/Est_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitslip" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/errcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/bitcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/slipcnt_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/psscan_flag_d" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<5>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<5>" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/wea" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_63" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_62" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_61" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_60" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_59" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_58" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_57" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_56" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_55" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_54" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_53" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_52" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_51" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_50" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_49" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_48" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_47" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_46" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_45" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_44" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_43" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_42" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_41" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_40" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_39" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_38" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_37" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_36" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_35" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_34" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_33" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_32" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_reply_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_cmd_update" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/WrConfirm" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_31" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_30" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_29" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_28" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_27" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_26" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_25" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_24" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_23" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_22" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_21" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_20" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_19" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_18" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_17" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_16" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dina_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/fee_flag" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/dcs_rpy_load" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_15" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/addra_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/ena" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/RamFlag" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder/u_DtcRamMgt/ReadConfirm_i" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_a/o" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_a/Mshreg_o" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/wren" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_1/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/wren" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_fsm_0/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout2_buf" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>"; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<18> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac" PINNAME CLIENTEMACRXCLIENTCLKIN; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<19> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac" PINNAME CLIENTEMACTXCLIENTCLKIN; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<135> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac" PINNAME HOSTCLK; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<174> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac" PINNAME PHYEMACGTXCLK; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<152> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i" PINNAME RXUSRCLK2; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<291> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i" PINNAME TXUSRCLK2; PIN u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<32> = BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<63> = BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<62> = BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<63> = BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<62> = BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<65> = BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<64> = BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<63> = BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen" PINNAME CLKARDCLKU; PIN u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<62> = BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen" PINNAME CLKARDCLKL; PIN u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<65> = BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen" PINNAME CLKBWRCLKU; PIN u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<64> = BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen" PINNAME CLKBWRCLKL; PIN u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<63> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen" PINNAME CLKARDCLKU; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<62> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen" PINNAME CLKARDCLKL; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<65> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen" PINNAME CLKBWRCLKU; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<64> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen" PINNAME CLKBWRCLKL; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<63> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen" PINNAME CLKARDCLKU; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<62> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen" PINNAME CLKARDCLKL; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<65> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen" PINNAME CLKBWRCLKU; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<64> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63> = BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62> = BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; PIN u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65> = BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKU; PIN u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64> = BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen" PINNAME CLKBWRCLKL; TIMEGRP u_dcs_eth_top/u_xgbe2_ll_wrapper/clk125_o = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/UdpSt_FSM_FFd1" BEL "u_sru_40dtc_top/u_udp_reply_mux/UdpSt_FSM_FFd2" BEL "u_sru_40dtc_top/u_udp_reply_mux/UdpSt_FSM_FFd3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_sw_wr_good_frame" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_sw_wr_data_valid" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_dst_rdy_n" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_sw_wr_enable" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/fifo_cs" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_FlashToUDP/u_UDPSCConv/st_FSM_FFd2" BEL "u_FlashToUDP/u_UDPSCConv/FifoWrSt_FSM_FFd1" BEL "u_FlashToUDP/u_UDPSCConv/st_FSM_FFd1" BEL "u_FlashToUDP/u_UDPSCConv/FifoWrSt_FSM_FFd3" BEL "u_FlashToUDP/u_UDPSCConv/FifoWrSt_FSM_FFd2" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_7" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_6" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_5" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_4" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_3" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_2" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_1" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_0" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_good_frame" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_71" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_70" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_69" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_68" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_67" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_66" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_65" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_64" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_15" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_14" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_13" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_12" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_11" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_10" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_9" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_8" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_7" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_6" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_5" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_4" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_3" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_2" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_1" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_0" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_valid" BEL "u_FlashToUDP/u_UDPSCConv/dcs_wr_enable" BEL "u_FlashToUDP/u_UDPSCConv/sctx_txdatardy" BEL "u_FlashToUDP/u_UDPSCConv/sctx_ack" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "SF1311_wg_cy<6>_FRB" BEL "u_FlashToUDP/udp_rx_dv_iiiii" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_5" BEL "u_FlashToUDP/udp_rxd_iiiii_5" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_7" BEL "u_FlashToUDP/udp_rxd_iiiii_7" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_6" BEL "u_FlashToUDP/udp_rxd_iiiii_6" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_4" BEL "u_FlashToUDP/udp_rxd_iiiii_4" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_3" BEL "u_FlashToUDP/udp_rxd_iiiii_3" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_2" BEL "u_FlashToUDP/udp_rxd_iiiii_2" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_1" BEL "u_FlashToUDP/udp_rxd_iiiii_1" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_0" BEL "u_FlashToUDP/udp_rxd_iiiii_0" BEL "u_FlashToUDP/Mshreg_udp_rx_dv_iiii" BEL "u_FlashToUDP/udp_rx_dv_iiii" BEL "spare<9>" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_41" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_42" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_43" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_44" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_45" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_46" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_47" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_48" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_49" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_50" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_51" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_52" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_53" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_54" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_55" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_56" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_57" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_58" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_59" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_60" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_61" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_62" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_63" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_64" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_65" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_66" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_67" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_68" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_69" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_70" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_71" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_72" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_73" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_74" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_75" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_76" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_77" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_78" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_79" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_80" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_81" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_82" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_83" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_84" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_85" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_86" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_87" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_88" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_89" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_FlashToUDP/u_UDPSCConv/synch_125/o" BEL "u_FlashToUDP/u_UDPSCConv/synch_125/Mshreg_o" BEL "u_FlashToUDP/u_UDPSCConv/synch_rd/o" BEL "u_FlashToUDP/u_UDPSCConv/synch_rd/Mshreg_o" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/u_udp_reply_mux/synch_reset/o" BEL "u_sru_40dtc_top/u_udp_reply_mux/synch_reset/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_dcs_eth_top/u_arp_reply_fsm/ArpSt_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_ch_sel" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_rd_dst_rdy_n" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_12" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_13" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_14" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_15" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_16" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_17" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_18" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_19" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_20" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_21" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_22" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_23" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_24" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_25" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_26" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_27" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_28" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_29" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_30" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_31" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_32" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_33" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_34" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_35" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_36" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_37" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_38" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_39" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_40" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_41" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_42" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_43" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_44" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_45" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_46" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_47" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_48" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_49" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_50" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_51" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_52" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_53" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_54" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_55" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_56" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_57" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_58" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_59" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_60" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_61" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_62" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_63" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_64" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_65" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_66" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_67" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_68" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_69" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_70" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_71" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_72" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_73" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_74" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_75" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_76" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_77" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_78" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_79" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_80" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_81" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_82" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_83" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_84" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_85" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_86" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_87" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_88" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_89" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_90" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_91" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_92" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_93" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_94" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_95" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_96" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_97" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_98" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_99" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_100" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_101" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_102" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_103" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_104" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_105" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_106" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_107" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_108" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_109" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_110" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_111" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_112" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_113" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_114" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_115" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_116" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_117" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_118" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_119" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_120" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_121" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_122" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_123" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_124" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_125" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_126" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_127" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_128" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_129" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_130" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_131" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_132" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_133" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_134" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_135" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_136" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_137" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_138" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_139" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_140" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_141" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_142" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_143" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_144" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_145" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_146" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_147" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_148" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_149" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_150" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_151" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_152" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_153" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_154" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_155" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_156" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_157" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_158" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_159" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_160" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_161" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_162" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_163" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_164" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_165" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_166" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_167" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_168" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_169" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_170" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_171" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_172" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_173" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_174" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_175" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_176" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_177" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_178" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_179" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_180" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_181" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_182" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_183" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_184" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_185" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_186" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_187" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_188" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_189" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_190" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_191" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_192" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_193" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_194" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_195" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_196" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_197" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_198" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_199" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_200" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_201" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_202" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_203" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_204" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_205" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_206" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_207" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_208" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_209" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_210" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_211" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_212" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_213" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_214" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_215" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_216" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_217" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_218" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_219" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_220" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_221" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_222" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_223" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_good_frame" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_valid" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_wr_enable" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/ArpSt_FSM_FFd2" BEL "u_dcs_eth_top/u_arp_reply_fsm/ArpSt_FSM_FFd1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/fifo_cs_i" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/fifo_cs" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/fifo_cs" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rx_dv" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_12" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_13" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_14" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_15" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/UdpProcessed" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_wr_enable" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_valid" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_good_frame" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IcmpReplySent" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/ip_rd_enable" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/ip_rd_ack" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/rx_frame_processed" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_12" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_13" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_14" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_15" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_16" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_17" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_18" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_19" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_20" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_21" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_22" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_23" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_24" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_25" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_26" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_27" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_28" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_29" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_30" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_31" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_32" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_33" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_34" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_35" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_36" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_37" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_38" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_39" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_40" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_41" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_42" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_43" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_44" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_45" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_46" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_47" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IpSt_FSM_FFd2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IpSt_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_cnt_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_cnt_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_cnt_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_cnt_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IpSt_FSM_FFd1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_12" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_13" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_14" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_15" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IcmpSt_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/UdpSt_FSM_FFd2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/UdpSt_FSM_FFd1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IcmpSt_FSM_FFd2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IcmpSt_FSM_FFd1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_12" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_13" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_14" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_15" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_16" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_17" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_18" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_19" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_20" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_21" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_22" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_23" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_24" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_25" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_26" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_27" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_28" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_29" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_30" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_31" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_32" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_33" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_34" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_35" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_36" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_37" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_38" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_39" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_40" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_41" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_42" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_43" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_44" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_45" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_46" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_47" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_48" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_49" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_50" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_51" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_52" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_53" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_54" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_55" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_56" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_57" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_58" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_59" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_60" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_61" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_62" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_63" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_64" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_65" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_66" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_67" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_68" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_69" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_70" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_71" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_72" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_73" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_74" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_75" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_76" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_77" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_78" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_79" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_80" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_81" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_82" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_83" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_84" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_85" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_86" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_87" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_88" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_89" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_90" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_91" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_92" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_93" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_94" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_95" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_96" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_97" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_98" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_99" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_100" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_101" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_102" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_103" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_104" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_105" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_106" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_107" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_108" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_109" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_110" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_111" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_112" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_113" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_114" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_115" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_116" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_117" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_118" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_119" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_120" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_121" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_122" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_123" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_124" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_125" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_126" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_127" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_128" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_129" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_130" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_131" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_132" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_133" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_134" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_135" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_136" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_137" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_138" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_139" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_140" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_141" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_142" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_143" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_144" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_145" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_146" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_147" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_148" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_149" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_150" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_151" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_152" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_153" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_154" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_155" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_156" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_157" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_158" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_159" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_req" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_good_frame" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_12" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_13" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_14" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_15" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_valid" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_wr_enable" BEL "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/fifo_cs_i" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/fifo_cs" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_0" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_2" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_3" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_4" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_5" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_6" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_sw_wr_enable" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_tx_rd_dst_rdy_n" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_sw_wr_data_valid" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_sw_wr_good_frame" BEL "u_dcs_eth_top/u_udp_reply_mux/UdpSt_FSM_FFd3" BEL "u_dcs_eth_top/u_udp_reply_mux/UdpSt_FSM_FFd2" BEL "u_dcs_eth_top/u_udp_reply_mux/UdpSt_FSM_FFd1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/fifo_cs_i" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/fifo_cs" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL 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"u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL 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"u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_dcs_eth_top/u_udp_reply_mux/synch_reset/o" BEL "u_dcs_eth_top/u_udp_reply_mux/synch_reset/Mshreg_o" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<15>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<14>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<13>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<12>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<11>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<10>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<9>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<8>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<7>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<6>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<5>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<4>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<3>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<2>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<1>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<0>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_data_pipe_st_FSM_FFd2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_data_pipe_st_FSM_FFd1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_req" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_frame" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/udp_frame" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/RxllNewByte" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_47" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_46" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_45" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_44" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_43" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_42" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_41" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_40" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_39" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_38" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_37" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_36" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_35" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_34" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_33" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_32" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_47" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_46" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_45" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_44" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_43" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_42" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_41" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_40" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_39" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_38" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_37" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_36" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_35" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_34" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_33" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_32" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_47" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_46" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_45" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_44" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_43" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_42" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_41" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_40" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_39" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_38" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_37" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_36" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_35" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_34" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_33" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_32" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/CheckSumReset" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_47" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_46" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_45" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_44" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_43" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_42" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_41" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_40" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_39" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_38" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_37" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_36" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_35" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_34" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_33" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_32" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_dst_rdy_n_i" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpDataDv" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_sof_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_fifo_full" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_tran_frame_tog" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_5_BRB3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_5_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_4_BRB2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_4_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_3_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_2_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_9_BRB4" BEL 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"u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_state_FSM_FFd4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_eof" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_col_window_expire" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_col_window_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_col_window_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_transmit_frame" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/frame_in_fifo" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_tran_frame_delay" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_tran_frame_sync" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_txfer_tog_delay" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_txfer_tog_sync" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/frame_in_fifo_sync" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_bram_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_txfer_tog" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_tran_frame_tog" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_sof_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_fifo_status_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_fifo_status_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_fifo_status_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_fifo_status_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_accept_bram" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_valid" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_col_window_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_col_window_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_enable_delay2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_accept_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_accept_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frame_in_fifo" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_state_reg" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_txfer_tog" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_eof_reg" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_enable_delay" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checkState" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_reset_i" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/bufg_clk125" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/resetdone_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_reset_i" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_reset_i" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_bad_frame_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_good_frame_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_valid_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/resetdone_tx_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/resetdone_rx_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_sof_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_fifo_full" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_retran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_tran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_ovflow_dst_rdy" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_col_window_expire" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_16_count_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_16_count_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_16_count_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_16_count_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_eof" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_col_window_expire" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_col_window_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_col_window_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_retransmit_frame" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_transmit_frame" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/frame_in_fifo" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_retran_frame_delay" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_retran_frame_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_tran_frame_delay" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_tran_frame_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_txfer_tog_delay" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_txfer_tog_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/frame_in_fifo_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_bram_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_txfer_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_retran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_tran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_sof_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_accept_bram" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_valid" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_col_window_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_col_window_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_enable_delay2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_accept_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_accept_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frame_in_fifo" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_state_reg" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_txfer_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_retransmit" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_drop_frame" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_eof_reg" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_enable_delay" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_bf_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_bf_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_gf_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_gf_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_valid_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_valid_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_eof_bram_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_fifo_full" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_store_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_eof_n_int" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_src_rdy_n_int" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_11" 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"u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_state_FSM_FFd3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_state_FSM_FFd1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_delay" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_dv_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_dv_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_sof_n_int" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/frame_in_fifo" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxrundisp_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxnotintable_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxdisperr_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxcharisk_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxchariscomma_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxclkcorcnt_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxclkcorcnt_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxclkcorcnt_r_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/txcharisk_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/txchardispval_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/txchardispmode_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/reset_r_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/reset_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/reset_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/reset_r_0" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<18>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<19>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<135>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<174>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<18>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<19>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<135>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<174>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<18>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<19>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<135>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<174>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<18>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<19>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<135>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<174>" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/resetdone_rx_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/resetdone_tx_r" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<152>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<291>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<152>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<291>" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/cnt_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/cnt_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/cnt_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/cnt_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/st_FSM_FFd1" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/st_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/st_FSM_FFd2" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_15" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_14" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_13" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_12" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_31" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_30" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_29" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_28" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_27" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_26" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_25" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_24" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_23" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_22" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_21" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_20" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_19" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_18" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_17" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_16" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_15" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_14" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_13" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_12" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_HeaderUpdate" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_143" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_142" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_141" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_140" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_139" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_138" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_137" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_136" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_135" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_134" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_133" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_132" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_131" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_130" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_129" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_128" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_127" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_126" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_125" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_124" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_123" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_122" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_121" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_120" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_119" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_118" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_117" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_116" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_115" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_114" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_113" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_112" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_111" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_110" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_109" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_108" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_107" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_106" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_105" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_104" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_103" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_102" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_101" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_100" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_99" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_98" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_97" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_96" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_95" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_94" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_93" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_92" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_91" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_90" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_89" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_88" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_87" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_86" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_85" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_84" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_83" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_82" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_81" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_80" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_79" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_78" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_77" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_76" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_75" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_74" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_73" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_72" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_71" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_70" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_69" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_68" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_67" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_66" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_65" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_64" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_63" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_62" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_61" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_60" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_59" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_58" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_57" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_56" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_55" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_54" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_53" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_52" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_51" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_50" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_49" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_48" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_47" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_46" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_45" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_44" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_43" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_42" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_41" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_40" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_39" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_38" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_37" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_36" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_35" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_34" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_33" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_32" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_31" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_30" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_29" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_28" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_27" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_26" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_25" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_24" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_23" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_22" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_21" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_20" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_19" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_18" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_17" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_16" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_15" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_14" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_13" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_12" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_ch_sel" BEL "u_dcs_eth_top/u_Eth_tx_fsm/EthReplySt_FSM_FFd2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/EthReplySt_FSM_FFd3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/EthReplySt_FSM_FFd1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_reply_rd_dst_rdy_n" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_111" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_110" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_109" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_108" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_107" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_106" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_105" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_104" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_103" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_102" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_101" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_100" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_99" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_98" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_97" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_96" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_95" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_94" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_93" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_92" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_91" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_90" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_89" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_88" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_87" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_86" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_85" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_84" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_83" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_82" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_81" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_80" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_79" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_78" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_77" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_76" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_75" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_74" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_73" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_72" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_71" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_70" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_69" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_68" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_67" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_66" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_65" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_64" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_63" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_62" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_61" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_60" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_59" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_58" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_57" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_56" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_55" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_54" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_53" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_52" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_51" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_50" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_49" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_48" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_47" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_46" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_45" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_44" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_43" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_42" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_41" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_40" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_39" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_38" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_37" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_36" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_35" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_34" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_33" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_32" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_31" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_30" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_29" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_28" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_27" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_26" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_25" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_24" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_23" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_22" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_21" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_20" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_19" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_18" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_17" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_16" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_good_frame" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_valid" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_enable" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_dv_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_valid_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_fifo_full" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_store_frame_tog" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_eof_n_int" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_src_rdy_n_int" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame_delay" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame_sync" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame_tog" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_fifo_status_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_fifo_status_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_fifo_status_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_fifo_status_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_dv_pipe_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_sof_n_int" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/frame_in_fifo" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdone" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/fifo_rd_en" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txstart" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txreq" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_5" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_6" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_7" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txcounter_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txcounter_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txcounter_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txcounter_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/state_FSM_FFd2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/state_FSM_FFd1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/Mshreg_txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_34" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_35" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_37" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_38" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_39" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD" BEL "u_FlashToUDP/u_scController/state_FSM_FFd1" BEL "u_FlashToUDP/u_scController/state_FSM_FFd2" BEL "u_FlashToUDP/u_scController/state_FSM_FFd4" BEL "u_FlashToUDP/u_scController/state_FSM_FFd3" BEL "u_FlashToUDP/u_scController/synch_125/o" BEL "u_FlashToUDP/u_scController/synch_125/Mshreg_o" BEL "u_FlashToUDP/u_scController/scRXqueue/request_i" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_10" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_9" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_8" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_7" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_6" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_5" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_4" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_3" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_2" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_1" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_0" BEL "u_FlashToUDP/u_scController/scRXqueue/lengthAck_i" BEL "u_FlashToUDP/u_scController/scRXqueue/error_flag" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_31" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_30" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_29" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_28" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_27" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_26" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_25" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_24" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_23" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_22" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_21" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_20" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_19" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_18" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_17" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_16" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_15" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_14" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_13" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_12" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_11" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_10" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_9" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_8" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_7" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_6" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_5" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_4" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_3" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_2" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_1" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_0" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_30" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_29" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_28" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_27" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_26" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_25" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_24" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_23" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_22" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_21" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_20" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_19" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_18" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_17" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_16" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_15" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_14" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_13" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_12" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_11" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_10" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_9" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_8" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_7" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_6" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_5" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_4" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_3" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_2" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_1" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_0" BEL "u_FlashToUDP/u_scController/scRXqueue/lengthAck2_i" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_31" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_30" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_29" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_28" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_27" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_26" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_25" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_24" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_23" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_22" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_21" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_20" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_19" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_18" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_17" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_16" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_15" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_14" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_13" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_12" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_11" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_15" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_14" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_13" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_12" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_11" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/error_7" BEL "u_FlashToUDP/u_scController/scRXqueue/error_6" BEL "u_FlashToUDP/u_scController/scRXqueue/error_5" BEL "u_FlashToUDP/u_scController/scRXqueue/error_4" BEL "u_FlashToUDP/u_scController/scRXqueue/error_3" BEL "u_FlashToUDP/u_scController/scRXqueue/error_2" BEL "u_FlashToUDP/u_scController/scRXqueue/lengthAck1_i" BEL "u_FlashToUDP/u_scController/scRXqueue/portAck1_i" BEL "u_FlashToUDP/u_scController/scRXqueue/portAck_i" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_30" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_29" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_28" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_27" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_26" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_25" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_24" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_23" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_22" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_21" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_20" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_19" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_18" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_17" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_16" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_15" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_14" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_13" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_12" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_11" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_15" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_14" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_13" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_12" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_11" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_15" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_14" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_13" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_12" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_11" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/rxdatavalid_q" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/Mshreg_txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/state_FSM_FFd1" BEL "u_FlashToUDP/u_scController/scRplyQueue/state_FSM_FFd2" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_15" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_14" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_13" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_15" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_14" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_13" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/df_rd_en" BEL "u_FlashToUDP/u_scController/scRplyQueue/txdone" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_15" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_14" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_13" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/pf_empty_q" BEL "u_FlashToUDP/u_scController/scRplyQueue/txstart" BEL "u_FlashToUDP/u_scController/scRplyQueue/pf_rd_en" BEL "u_FlashToUDP/u_scController/scRplyQueue/txreq" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/Mshreg_txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/rstn_synch[0]_dff_4_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/Mshreg_rstn_synch[0]_dff_4_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/state_FSM_FFd1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/state_FSM_FFd2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txcounter_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txcounter_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txcounter_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txcounter_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_7" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_6" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_5" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txreq" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/fifo_empty_q" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/fifo_rd_en" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txstart" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdone" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_34" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_35" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_37" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_38" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_39" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_dcs_cmddis/st_FSM_FFd2" BEL "u_dcs_cmddis/st_FSM_FFd3" BEL "u_dcs_cmddis/st_FSM_FFd1" BEL "u_dcs_cmddis/st_FSM_FFd5" BEL "u_dcs_cmddis/st_FSM_FFd4" BEL "u_dcs_cmddis/dcs_rx_dv_40" BEL "u_dcs_cmddis/dcs_rx_dv_39" BEL "u_dcs_cmddis/dcs_rx_dv_38" BEL "u_dcs_cmddis/dcs_rx_dv_37" BEL "u_dcs_cmddis/dcs_rx_dv_36" BEL "u_dcs_cmddis/dcs_rx_dv_35" BEL "u_dcs_cmddis/dcs_rx_dv_34" BEL "u_dcs_cmddis/dcs_rx_dv_33" BEL "u_dcs_cmddis/dcs_rx_dv_32" BEL "u_dcs_cmddis/dcs_rx_dv_31" BEL "u_dcs_cmddis/dcs_rx_dv_30" BEL "u_dcs_cmddis/dcs_rx_dv_29" BEL "u_dcs_cmddis/dcs_rx_dv_28" BEL "u_dcs_cmddis/dcs_rx_dv_27" BEL "u_dcs_cmddis/dcs_rx_dv_26" BEL "u_dcs_cmddis/dcs_rx_dv_25" BEL "u_dcs_cmddis/dcs_rx_dv_24" BEL "u_dcs_cmddis/dcs_rx_dv_23" BEL "u_dcs_cmddis/dcs_rx_dv_22" BEL "u_dcs_cmddis/dcs_rx_dv_21" BEL "u_dcs_cmddis/dcs_rx_dv_20" BEL "u_dcs_cmddis/dcs_rx_dv_19" BEL "u_dcs_cmddis/dcs_rx_dv_18" BEL "u_dcs_cmddis/dcs_rx_dv_17" BEL "u_dcs_cmddis/dcs_rx_dv_16" BEL "u_dcs_cmddis/dcs_rx_dv_15" BEL "u_dcs_cmddis/dcs_rx_dv_14" BEL "u_dcs_cmddis/dcs_rx_dv_13" BEL "u_dcs_cmddis/dcs_rx_dv_12" BEL "u_dcs_cmddis/dcs_rx_dv_11" BEL "u_dcs_cmddis/dcs_rx_dv_10" BEL "u_dcs_cmddis/dcs_rx_dv_9" BEL "u_dcs_cmddis/dcs_rx_dv_8" BEL "u_dcs_cmddis/dcs_rx_dv_7" BEL "u_dcs_cmddis/dcs_rx_dv_6" BEL "u_dcs_cmddis/dcs_rx_dv_5" BEL "u_dcs_cmddis/dcs_rx_dv_4" BEL "u_dcs_cmddis/dcs_rx_dv_3" BEL "u_dcs_cmddis/dcs_rx_dv_2" BEL "u_dcs_cmddis/dcs_rx_dv_1" BEL "u_dcs_cmddis/dcs_rx_dv_0" BEL "u_dcs_cmddis/dcs_rx_dv_i_0" BEL "u_dcs_cmddis/dcs_rx_dv_i_1" BEL "u_dcs_cmddis/dcs_rx_dv_i_2" BEL "u_dcs_cmddis/dcs_rx_dv_i_3" BEL "u_dcs_cmddis/dcs_rx_dv_i_4" BEL "u_dcs_cmddis/dcs_rx_dv_i_5" BEL "u_dcs_cmddis/dcs_rx_dv_i_7" BEL "u_dcs_cmddis/dcs_rx_dv_i_6" BEL "u_dcs_cmddis/dcs_rx_dv_i_8" BEL "u_dcs_cmddis/dcs_rx_dv_i_9" BEL "u_dcs_cmddis/dcs_rx_dv_i_10" BEL "u_dcs_cmddis/dcs_rx_dv_i_11" BEL "u_dcs_cmddis/dcs_rx_dv_i_12" BEL "u_dcs_cmddis/dcs_rx_dv_i_13" BEL "u_dcs_cmddis/dcs_rx_dv_i_14" BEL "u_dcs_cmddis/dcs_rx_dv_i_15" BEL "u_dcs_cmddis/dcs_rx_dv_i_20" BEL "u_dcs_cmddis/dcs_rx_dv_i_21" BEL "u_dcs_cmddis/dcs_rx_dv_i_22" BEL "u_dcs_cmddis/dcs_rx_dv_i_23" BEL "u_dcs_cmddis/dcs_rx_dv_i_25" BEL "u_dcs_cmddis/dcs_rx_dv_i_26" BEL "u_dcs_cmddis/dcs_rx_dv_i_24" BEL "u_dcs_cmddis/dcs_rx_dv_i_27" BEL "u_dcs_cmddis/dcs_rx_dv_i_16" BEL "u_dcs_cmddis/dcs_rx_dv_i_17" BEL "u_dcs_cmddis/dcs_rx_dv_i_18" BEL "u_dcs_cmddis/dcs_rx_dv_i_19" BEL "u_dcs_cmddis/dcs_rx_dv_i_28" BEL "u_dcs_cmddis/dcs_rx_dv_i_29" BEL "u_dcs_cmddis/dcs_rx_dv_i_30" BEL "u_dcs_cmddis/dcs_rx_dv_i_31" BEL "u_dcs_cmddis/dcs_rx_dv_i_32" BEL "u_dcs_cmddis/dcs_rx_dv_i_34" BEL "u_dcs_cmddis/dcs_rx_dv_i_35" BEL "u_dcs_cmddis/dcs_rx_dv_i_33" BEL "u_dcs_cmddis/dcs_rx_dv_i_36" BEL "u_dcs_cmddis/dcs_rx_dv_i_37" BEL "u_dcs_cmddis/dcs_rx_dv_i_38" BEL "u_dcs_cmddis/dcs_rx_dv_i_39" BEL "u_dcs_cmddis/dcs_rx_dv_i_40" BEL "u_dcs_cmddis/udp_rx_src_port_0" BEL "u_dcs_cmddis/udp_rx_src_port_1" BEL "u_dcs_cmddis/udp_rx_src_port_2" BEL "u_dcs_cmddis/udp_rx_src_port_4" BEL "u_dcs_cmddis/udp_rx_src_port_5" BEL "u_dcs_cmddis/udp_rx_src_port_3" BEL "u_dcs_cmddis/udp_rx_src_port_6" BEL "u_dcs_cmddis/udp_rx_src_port_7" BEL "u_dcs_cmddis/udp_rx_dst_port_0" BEL "u_dcs_cmddis/udp_rx_dst_port_1" BEL "u_dcs_cmddis/udp_rx_dst_port_2" BEL "u_dcs_cmddis/udp_rx_dst_port_3" BEL "u_dcs_cmddis/udp_rx_dst_port_5" BEL "u_dcs_cmddis/udp_rx_dst_port_6" BEL "u_dcs_cmddis/udp_rx_dst_port_4" BEL "u_dcs_cmddis/udp_rx_dst_port_7" BEL "u_dcs_cmddis/udp_rx_src_port_8" BEL "u_dcs_cmddis/udp_rx_src_port_9" BEL "u_dcs_cmddis/udp_rx_src_port_10" BEL "u_dcs_cmddis/udp_rx_src_port_11" BEL "u_dcs_cmddis/udp_rx_src_port_12" BEL "u_dcs_cmddis/udp_rx_src_port_13" BEL "u_dcs_cmddis/udp_rx_src_port_14" BEL "u_dcs_cmddis/udp_rx_src_port_15" BEL "u_dcs_cmddis/udp_rx_dst_port_8" BEL "u_dcs_cmddis/udp_rx_dst_port_9" BEL "u_dcs_cmddis/udp_rx_dst_port_10" BEL "u_dcs_cmddis/udp_rx_dst_port_11" BEL "u_dcs_cmddis/udp_rx_dst_port_12" BEL "u_dcs_cmddis/udp_rx_dst_port_14" BEL "u_dcs_cmddis/udp_rx_dst_port_15" BEL "u_dcs_cmddis/udp_rx_dst_port_13" BEL "u_dcs_cmddis/dcs_rxd_7" BEL "u_dcs_cmddis/dcs_rxd_6" BEL "u_dcs_cmddis/dcs_rxd_5" BEL "u_dcs_cmddis/dcs_rxd_4" BEL "u_dcs_cmddis/dcs_rxd_3" BEL "u_dcs_cmddis/dcs_rxd_2" BEL "u_dcs_cmddis/dcs_rxd_1" BEL "u_dcs_cmddis/dcs_rxd_0" BEL "u_dcs_cmddis/synch_udprx/o" BEL "u_dcs_cmddis/synch_udprx/Mshreg_o" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM100_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM100_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM100_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM100_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM101_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM101_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM101_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM101_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM102_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM102_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM102_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM102_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM103_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM103_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM103_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM103_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM104_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM104_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM104_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM104_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM105_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM105_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM105_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM105_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM106_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM106_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM106_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM106_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM107_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM107_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM107_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM107_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM108_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM108_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM108_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM108_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM109_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM109_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM109_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM109_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM110_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM110_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM110_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM110_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM111_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM111_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM111_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM111_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM112_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM112_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM112_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM112_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM113_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM113_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM113_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM113_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM114_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM114_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM114_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM114_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM115_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM115_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM115_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM115_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM116_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM116_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM116_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM116_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM117_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM117_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM117_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM117_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM118_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM118_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM118_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM118_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM119_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM119_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM119_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM119_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM120_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM120_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM120_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM120_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM121_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM121_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM121_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM121_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM122_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM122_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM122_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM122_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM123_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM123_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM123_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM123_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM124_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM124_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM124_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM124_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM125_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM125_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM125_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM125_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM126_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM126_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM126_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM126_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM127_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM127_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM127_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM127_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM128_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM128_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM128_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM128_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM129_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM129_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM129_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM129_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM130_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM130_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM130_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM130_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM131_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM131_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM131_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM131_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM132_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM132_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM132_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM132_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM133_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM133_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM133_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM133_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM134_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM134_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM134_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM134_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM135_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM135_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM135_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM135_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM136_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM136_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM136_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM136_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM137_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM137_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM137_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM137_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM138_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM138_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM138_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM138_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM139_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM139_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM139_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM139_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM140_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM140_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM140_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM140_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM141_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM141_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM141_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM141_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM142_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM142_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM142_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM142_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM143_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM143_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM143_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM143_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM144_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM144_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM144_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM144_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM145_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM145_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM145_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM145_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM146_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM146_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM146_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM146_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM147_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM147_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM147_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM147_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM148_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM148_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM148_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM148_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM149_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM149_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM149_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM149_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM150_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM150_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM150_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM150_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM151_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM151_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM151_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM151_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM152_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM152_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM152_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM152_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM153_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM153_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM153_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM153_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM154_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM154_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM154_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM154_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM155_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM155_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM155_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM155_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM156_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM156_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM156_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM156_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM157_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM157_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM157_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM157_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM158_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM158_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM158_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM158_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM159_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM159_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM159_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM159_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM160_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM160_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM160_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM160_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM161_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM161_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM161_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM161_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM162_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM162_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM162_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM162_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM163_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM163_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM163_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM163_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM164_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM164_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM164_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM164_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM165_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM165_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM165_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM165_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM166_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM166_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM166_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM166_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM167_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM167_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM167_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM167_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM168_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM168_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM168_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM168_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM169_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM169_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM169_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM169_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM170_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM170_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM170_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM170_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM171_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM171_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM171_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM171_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM172_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM172_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM172_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM172_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM173_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM173_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM173_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM173_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM174_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM174_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM174_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM174_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM175_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM175_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM175_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM175_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM176_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM176_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM176_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM176_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM177_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM177_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM177_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM177_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM178_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM178_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM178_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM178_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM179_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM179_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM179_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM179_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM180_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM180_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM180_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM180_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM181_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM181_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM181_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM181_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM182_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM182_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM182_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM182_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM183_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM183_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM183_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM183_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM184_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM184_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM184_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM184_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM185_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM185_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM185_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM185_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM186_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM186_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM186_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM186_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM187_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM187_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM187_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM187_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM188_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM188_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM188_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM188_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM189_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM189_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM189_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM189_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM190_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM190_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM190_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM190_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM191_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM191_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM191_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM191_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM192_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM192_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM192_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM192_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM97_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM97_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM97_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM97_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM98_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM98_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM98_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM98_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM99_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM99_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM99_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM99_RAMD" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<32>" PIN "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<63>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<62>" PIN "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<63>" PIN "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<62>" PIN "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<65>" PIN "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<63>" PIN "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<62>" PIN "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<65>" PIN "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<64>" PIN "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<63>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<62>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<65>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<64>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<63>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<62>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<65>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>"; TIMEGRP u_xgbe2_ll_wrapper_clk125_o = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_cnt_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/UdpSt_FSM_FFd1" BEL "u_sru_40dtc_top/u_udp_reply_mux/UdpSt_FSM_FFd2" BEL "u_sru_40dtc_top/u_udp_reply_mux/UdpSt_FSM_FFd3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_sw_wr_good_frame" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_sw_wr_data_valid" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_dst_rdy_n" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_sw_wr_enable" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/ip_tx_rd_data_pipe_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/fifo_cs" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "u_FlashToUDP/u_UDPSCConv/st_FSM_FFd2" BEL "u_FlashToUDP/u_UDPSCConv/FifoWrSt_FSM_FFd1" BEL "u_FlashToUDP/u_UDPSCConv/st_FSM_FFd1" BEL "u_FlashToUDP/u_UDPSCConv/FifoWrSt_FSM_FFd3" BEL "u_FlashToUDP/u_UDPSCConv/FifoWrSt_FSM_FFd2" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_7" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_6" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_5" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_4" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_3" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_2" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_1" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_0" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_good_frame" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_71" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_70" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_69" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_68" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_67" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_66" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_65" BEL "u_FlashToUDP/u_UDPSCConv/udp_header_reg_64" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_15" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_14" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_13" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_12" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_11" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_10" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_9" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_8" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_7" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_6" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_5" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_4" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_3" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_2" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_1" BEL "u_FlashToUDP/u_UDPSCConv/clkcnt_0" BEL "u_FlashToUDP/u_UDPSCConv/dcs_rx_data_valid" BEL "u_FlashToUDP/u_UDPSCConv/dcs_wr_enable" BEL "u_FlashToUDP/u_UDPSCConv/sctx_txdatardy" BEL "u_FlashToUDP/u_UDPSCConv/sctx_ack" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/fifo_cs" BEL "SF1311_wg_cy<6>_FRB" BEL "u_FlashToUDP/udp_rx_dv_iiiii" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_5" BEL "u_FlashToUDP/udp_rxd_iiiii_5" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_7" BEL "u_FlashToUDP/udp_rxd_iiiii_7" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_6" BEL "u_FlashToUDP/udp_rxd_iiiii_6" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_4" BEL "u_FlashToUDP/udp_rxd_iiiii_4" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_3" BEL "u_FlashToUDP/udp_rxd_iiiii_3" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_2" BEL "u_FlashToUDP/udp_rxd_iiiii_2" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_1" BEL "u_FlashToUDP/udp_rxd_iiiii_1" BEL "u_FlashToUDP/Mshreg_udp_rxd_iiiii_0" BEL "u_FlashToUDP/udp_rxd_iiiii_0" BEL "u_FlashToUDP/Mshreg_udp_rx_dv_iiii" BEL "u_FlashToUDP/udp_rx_dv_iiii" BEL "spare<9>" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_41" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_42" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_43" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_44" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_45" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_46" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_47" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_48" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_49" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_50" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_51" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_52" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_53" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_54" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_55" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_56" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_57" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_58" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_59" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_60" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_61" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_62" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_63" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_64" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_65" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_66" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_67" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_68" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_69" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_70" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_71" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_72" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_73" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_74" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_75" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_76" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_77" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_78" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_79" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_80" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_81" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_82" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_83" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_84" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_85" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_86" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_87" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_88" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_89" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_FlashToUDP/u_UDPSCConv/synch_125/o" BEL "u_FlashToUDP/u_UDPSCConv/synch_125/Mshreg_o" BEL "u_FlashToUDP/u_UDPSCConv/synch_rd/o" BEL "u_FlashToUDP/u_UDPSCConv/synch_rd/Mshreg_o" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/u_udp_reply_mux/synch_reset/o" BEL "u_sru_40dtc_top/u_udp_reply_mux/synch_reset/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/synch_rd/Mshreg_o" BEL "u_dcs_eth_top/u_arp_reply_fsm/ArpSt_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_ch_sel" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_rd_dst_rdy_n" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_12" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_13" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_14" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_15" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_16" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_17" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_18" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_19" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_20" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_21" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_22" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_23" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_24" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_25" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_26" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_27" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_28" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_29" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_30" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_31" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_32" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_33" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_34" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_35" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_36" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_37" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_38" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_39" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_40" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_41" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_42" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_43" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_44" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_45" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_46" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_47" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_48" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_49" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_50" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_51" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_52" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_53" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_54" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_55" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_56" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_57" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_58" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_59" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_60" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_61" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_62" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_63" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_64" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_65" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_66" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_67" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_68" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_69" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_70" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_71" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_72" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_73" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_74" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_75" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_76" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_77" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_78" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_79" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_80" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_81" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_82" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_83" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_84" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_85" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_86" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_87" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_88" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_89" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_90" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_91" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_92" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_93" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_94" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_95" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_96" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_97" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_98" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_99" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_100" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_101" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_102" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_103" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_104" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_105" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_106" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_107" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_108" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_109" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_110" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_111" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_112" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_113" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_114" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_115" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_116" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_117" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_118" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_119" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_120" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_121" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_122" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_123" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_124" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_125" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_126" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_127" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_128" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_129" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_130" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_131" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_132" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_133" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_134" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_135" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_136" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_137" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_138" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_139" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_140" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_141" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_142" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_143" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_144" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_145" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_146" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_147" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_148" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_149" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_150" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_151" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_152" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_153" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_154" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_155" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_156" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_157" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_158" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_159" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_160" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_161" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_162" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_163" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_164" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_165" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_166" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_167" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_168" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_169" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_170" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_171" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_172" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_173" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_174" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_175" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_176" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_177" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_178" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_179" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_180" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_181" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_182" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_183" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_184" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_185" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_186" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_187" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_188" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_189" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_190" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_191" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_192" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_193" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_194" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_195" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_196" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_197" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_198" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_199" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_200" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_201" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_202" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_203" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_204" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_205" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_206" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_207" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_208" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_209" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_210" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_211" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_212" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_213" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_214" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_215" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_216" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_217" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_218" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_219" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_220" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_221" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_222" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_pipe_223" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_good_frame" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_tx_data_valid" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_wr_enable" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_cnt_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/ArpSt_FSM_FFd2" BEL "u_dcs_eth_top/u_arp_reply_fsm/ArpSt_FSM_FFd1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/fifo_cs_i" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/fifo_cs" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/fifo_cs" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/fifo_cs_i" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rxd_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/udp_rx_dv" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_12" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_13" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_14" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_length_15" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/UdpProcessed" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_wr_enable" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_valid" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_good_frame" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IcmpReplySent" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/ip_rd_enable" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/ip_rd_ack" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/rx_frame_processed" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_12" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_13" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_14" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_15" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_16" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_17" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_18" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_19" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_20" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_21" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_22" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_23" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_24" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_25" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_26" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_27" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_28" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_29" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_30" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_31" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_32" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_33" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_34" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_35" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_36" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_37" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_38" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_39" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_40" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_41" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_42" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_43" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_44" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_45" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_46" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_header_reg_47" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_data_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IpSt_FSM_FFd2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IpSt_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_cnt_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_cnt_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_cnt_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_cnt_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IpSt_FSM_FFd1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_12" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_13" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_14" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/data_cnt_15" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IcmpSt_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/UdpSt_FSM_FFd2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/UdpSt_FSM_FFd1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IcmpSt_FSM_FFd2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/IcmpSt_FSM_FFd1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_12" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_13" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_14" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_15" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_16" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_17" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_18" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_19" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_20" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_21" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_22" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_23" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_24" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_25" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_26" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_27" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_28" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_29" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_30" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_31" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_32" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_33" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_34" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_35" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_36" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_37" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_38" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_39" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_40" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_41" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_42" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_43" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_44" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_45" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_46" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_47" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_48" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_49" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_50" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_51" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_52" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_53" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_54" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_55" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_56" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_57" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_58" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_59" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_60" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_61" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_62" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_63" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_64" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_65" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_66" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_67" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_68" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_69" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_70" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_71" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_72" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_73" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_74" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_75" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_76" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_77" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_78" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_79" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_80" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_81" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_82" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_83" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_84" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_85" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_86" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_87" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_88" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_89" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_90" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_91" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_92" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_93" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_94" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_95" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_96" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_97" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_98" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_99" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_100" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_101" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_102" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_103" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_104" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_105" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_106" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_107" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_108" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_109" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_110" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_111" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_112" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_113" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_114" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_115" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_116" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_117" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_118" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_119" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_120" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_121" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_122" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_123" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_124" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_125" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_126" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_127" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_128" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_129" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_130" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_131" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_132" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_133" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_134" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_135" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_136" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_137" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_138" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_139" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_140" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_141" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_142" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_143" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_144" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_145" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_146" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_147" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_148" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_149" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_150" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_151" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_152" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_153" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_154" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_155" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_156" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_157" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_158" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_pipe_159" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_header_req" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_good_frame" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_12" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_13" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_14" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_total_len_15" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_tx_data_valid" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_wr_enable" BEL "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_cnt_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ipSt_FSM_FFd1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/fifo_cs_i" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/fifo_cs" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_0" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_2" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_3" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_4" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_5" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_6" BEL "u_dcs_eth_top/u_udp_reply_mux/ip_tx_rd_data_pipe_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_sw_wr_enable" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_tx_rd_fifo_addr_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_tx_rd_dst_rdy_n" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_sw_wr_data_valid" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_sw_wr_good_frame" BEL "u_dcs_eth_top/u_udp_reply_mux/UdpSt_FSM_FFd3" BEL "u_dcs_eth_top/u_udp_reply_mux/UdpSt_FSM_FFd2" BEL "u_dcs_eth_top/u_udp_reply_mux/UdpSt_FSM_FFd1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_cnt_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/fifo_cs_i" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/fifo_cs" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL 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"u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL 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BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL 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"u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_data_out_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_data_bram_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_valid_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_full" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_store_frame_tog" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_eof_n_int" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_src_rdy_n_int" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_frames_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_addr_diff_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_delay" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_sync" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_addr_gray_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_store_frame_tog" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_fifo_status_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_dv_pipe_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_11" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_10" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_9" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_8" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_7" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_6" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_5" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_4" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_3" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_2" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_1" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/wr_start_addr_0" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/rd_sof_n_int" BEL "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/frame_in_fifo" BEL "u_dcs_eth_top/u_udp_reply_mux/synch_reset/o" BEL "u_dcs_eth_top/u_udp_reply_mux/synch_reset/Mshreg_o" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<15>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<14>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<13>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<12>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<11>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<10>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<9>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<8>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<7>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<6>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<5>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<4>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<3>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<2>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<1>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt[15]_GND_18_o_add_15_OUT<0>_FRB" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/EthSt_FSM_FFd3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSt_FSM_FFd2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_data_pipe_st_FSM_FFd2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_data_pipe_st_FSM_FFd1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_req" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_frame" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/udp_frame" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_cnt_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IPFrameLen_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpData_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/RxllNewByte" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_receiver_ip_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_ip_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_47" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_46" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_45" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_44" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_43" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_42" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_41" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_40" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_39" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_38" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_37" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_36" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_35" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_34" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_33" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_32" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_sender_mac_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/icmp_type_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_ip_i_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/arp_op_code_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_ip_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/ip_protocol_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/eth_type_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_47" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_46" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_45" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_44" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_43" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_42" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_41" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_40" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_39" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_38" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_37" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_36" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_35" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_34" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_33" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_32" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/remote_mac_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_47" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_46" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_45" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_44" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_43" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_42" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_41" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_40" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_39" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_38" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_37" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_36" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_35" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_34" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_33" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_32" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/local_mac_i_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/CheckSumReset" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_47" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_46" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_45" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_44" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_43" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_42" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_41" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_40" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_39" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_38" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_37" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_36" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_35" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_34" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_33" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_32" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_31" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_30" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_29" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_28" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_27" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_26" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_25" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_24" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_23" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_22" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_21" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_20" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_19" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_18" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_17" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_data_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/rx_ll_dst_rdy_n_i" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpDataDv" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_sof_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_fifo_full" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_tran_frame_tog" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_5_BRB3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_5_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_4_BRB2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_4_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_3_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_2_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_9_BRB4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_9_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_8_BRB3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_8_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_11_BRB2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_11_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_7_BRB2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_7_BRB1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_7_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_10_BRB1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_10_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_6_BRB1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_6_BRB0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_ovflow_dst_rdy" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_col_window_expire" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frames_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_16_count_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_16_count_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_16_count_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_16_count_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_slot_timer_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_state_FSM_FFd4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_diff_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_eof" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_data_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_col_window_expire" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_col_window_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_rd_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_col_window_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_transmit_frame" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/frame_in_fifo" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_tran_frame_delay" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_tran_frame_sync" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_txfer_tog_delay" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_txfer_tog_sync" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/frame_in_fifo_sync" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_bram_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_bram_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_txfer_tog" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_tran_frame_tog" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_addr_txfer_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_start_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_sof_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_fifo_status_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_fifo_status_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_fifo_status_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_fifo_status_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_accept_bram" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_dec_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_start_addr_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/tx_data_valid" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_col_window_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_col_window_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_enable_delay2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_accept_pipe_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_accept_pipe_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_frame_in_fifo" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_eof_state_reg" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/wr_data_pipe<0>_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_txfer_tog" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_eof_reg" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/rd_enable_delay" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_16" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_15" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_14" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_13" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_12" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_11" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_10" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_9" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_8" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checksumC2_0" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/checkState" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_7" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_6" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_5" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_4" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_3" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_2" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_1" BEL "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/IcmpChkSumCalUnit/MSB_latch_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_reset_i" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/bufg_clk125" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/ll_pre_reset_i_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/resetdone_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_reset_i" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_reset_i" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/tx_pre_reset_i_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_pre_reset_i_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_r_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_bad_frame_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_good_frame_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/rx_data_valid_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/resetdone_tx_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/resetdone_rx_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_sof_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_fifo_full" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_retran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_tran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_ovflow_dst_rdy" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_col_window_expire" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frames_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_16_count_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_16_count_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_16_count_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_16_count_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_slot_timer_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_eof" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_data_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_col_window_expire" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_col_window_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_col_window_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_retransmit_frame" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_transmit_frame" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/frame_in_fifo" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_retran_frame_delay" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_retran_frame_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_tran_frame_delay" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_tran_frame_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_txfer_tog_delay" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_txfer_tog_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/frame_in_fifo_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_bram_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_bram_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_txfer_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_retran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_tran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_addr_txfer_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_sof_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_accept_bram" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_dec_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_start_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/tx_data_valid" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_col_window_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_col_window_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_enable_delay2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_accept_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_accept_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_frame_in_fifo" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_eof_state_reg" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_data_pipe<0>_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_txfer_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_retransmit" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_drop_frame" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_eof_reg" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_enable_delay" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_data_out_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_data_bram_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_data_bram_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_bf_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_bf_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_gf_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_wr_gf_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_valid_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/Mshreg_rd_valid_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_eof_bram_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_fifo_full" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_store_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_eof_n_int" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_src_rdy_n_int" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_frames_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_state_FSM_FFd3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_state_FSM_FFd1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_addr_diff_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_delay" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_start_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_addr_gray_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_dv_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_dv_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_sof_n_int" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/frame_in_fifo" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxrundisp_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxnotintable_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxdisperr_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxcharisk_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxchariscomma_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_rx_data_r_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxclkcorcnt_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxclkcorcnt_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/rxclkcorcnt_r_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/txcharisk_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/txchardispval_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/txchardispmode_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/mgt_tx_data_r_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/reset_r_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/reset_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/reset_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/reset_r_0" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<18>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<19>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<135>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<174>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<18>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<19>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<135>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<174>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<18>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<19>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<135>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<174>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<18>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<19>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<135>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/xgbe2_inst/v6_emac_pins<174>" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/resetdone_rx_r" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/resetdone_tx_r" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<152>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<291>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<152>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<291>" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/cnt_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/cnt_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/cnt_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/cnt_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/st_FSM_FFd1" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/st_FSM_FFd3" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/st_FSM_FFd2" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_15" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_14" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_13" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_12" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_31" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_30" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_29" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_28" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_27" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_26" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_25" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_24" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_23" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_22" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_21" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_20" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_19" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_18" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_17" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_16" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_15" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_14" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_13" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_12" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/chk_sum_i_0" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_HeaderUpdate" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_143" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_142" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_141" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_140" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_139" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_138" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_137" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_136" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_135" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_134" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_133" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_132" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_131" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_130" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_129" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_128" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_127" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_126" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_125" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_124" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_123" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_122" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_121" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_120" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_119" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_118" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_117" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_116" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_115" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_114" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_113" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_112" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_111" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_110" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_109" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_108" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_107" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_106" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_105" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_104" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_103" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_102" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_101" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_100" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_99" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_98" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_97" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_96" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_95" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_94" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_93" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_92" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_91" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_90" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_89" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_88" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_87" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_86" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_85" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_84" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_83" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_82" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_81" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_80" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_79" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_78" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_77" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_76" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_75" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_74" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_73" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_72" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_71" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_70" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_69" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_68" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_67" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_66" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_65" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_64" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_63" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_62" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_61" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_60" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_59" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_58" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_57" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_56" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_55" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_54" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_53" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_52" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_51" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_50" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_49" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_48" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_47" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_46" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_45" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_44" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_43" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_42" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_41" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_40" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_39" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_38" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_37" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_36" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_35" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_34" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_33" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_32" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_31" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_30" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_29" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_28" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_27" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_26" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_25" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_24" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_23" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_22" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_21" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_20" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_19" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_18" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_17" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_16" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_15" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_14" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_13" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_12" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_11" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_10" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_9" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_8" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_7" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_6" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_5" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_4" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_3" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_2" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_1" BEL "u_dcs_eth_top/u_ip_reply_fsm/u_ip_hchksum/ip_header_reg_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_ch_sel" BEL "u_dcs_eth_top/u_Eth_tx_fsm/EthReplySt_FSM_FFd2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/EthReplySt_FSM_FFd3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/EthReplySt_FSM_FFd1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_reply_rd_dst_rdy_n" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/cnt_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_111" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_110" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_109" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_108" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_107" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_106" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_105" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_104" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_103" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_102" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_101" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_100" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_99" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_98" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_97" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_96" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_95" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_94" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_93" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_92" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_91" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_90" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_89" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_88" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_87" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_86" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_85" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_84" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_83" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_82" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_81" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_80" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_79" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_78" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_77" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_76" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_75" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_74" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_73" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_72" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_71" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_70" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_69" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_68" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_67" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_66" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_65" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_64" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_63" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_62" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_61" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_60" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_59" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_58" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_57" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_56" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_55" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_54" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_53" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_52" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_51" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_50" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_49" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_48" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_47" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_46" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_45" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_44" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_43" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_42" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_41" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_40" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_39" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_38" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_37" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_36" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_35" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_34" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_33" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_32" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_31" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_30" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_29" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_28" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_27" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_26" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_25" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_24" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_23" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_22" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_21" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_20" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_19" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_18" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_17" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_16" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/eth_header_reg_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_good_frame" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_data_valid" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_wr_enable" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_data_out_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_data_out_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_data_bram_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_data_bram_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_good_frame_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_dv_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_wr_dv_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_valid_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/Mshreg_rd_valid_pipe_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_fifo_full" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_store_frame_tog" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_eof_n_int" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_src_rdy_n_int" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_frames_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_state_FSM_FFd2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_state_FSM_FFd1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_state_FSM_FFd2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_state_FSM_FFd3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_state_FSM_FFd3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_addr_diff_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_rd_addr_gray_sync_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame_delay" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame_sync" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_addr_gray_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_store_frame_tog" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_fifo_status_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_fifo_status_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_fifo_status_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_fifo_status_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_good_frame_pipe_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_dv_pipe_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_11" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_10" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_9" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_8" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_7" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_6" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_5" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_4" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_3" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_2" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_1" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/wr_start_addr_0" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/rd_sof_n_int" BEL "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/frame_in_fifo" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_11" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdone" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/fifo_rd_en" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txstart" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txreq" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_5" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_6" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdata_7" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txcounter_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txcounter_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txcounter_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txcounter_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/state_FSM_FFd2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/state_FSM_FFd1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/Mshreg_txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_34" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_35" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_37" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_38" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_39" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMC" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD_D1" BEL "u_FlashToUDP/u_scController/scRXErrorQueue/rxerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD" BEL "u_FlashToUDP/u_scController/state_FSM_FFd1" BEL "u_FlashToUDP/u_scController/state_FSM_FFd2" BEL "u_FlashToUDP/u_scController/state_FSM_FFd4" BEL "u_FlashToUDP/u_scController/state_FSM_FFd3" BEL "u_FlashToUDP/u_scController/synch_125/o" BEL "u_FlashToUDP/u_scController/synch_125/Mshreg_o" BEL "u_FlashToUDP/u_scController/scRXqueue/request_i" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_10" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_9" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_8" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_7" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_6" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_5" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_4" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_3" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_2" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_1" BEL "u_FlashToUDP/u_scController/scRXqueue/wrcounter_0" BEL "u_FlashToUDP/u_scController/scRXqueue/lengthAck_i" BEL "u_FlashToUDP/u_scController/scRXqueue/error_flag" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_31" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_30" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_29" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_28" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_27" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_26" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_25" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_24" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_23" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_22" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_21" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_20" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_19" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_18" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_17" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_16" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_15" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_14" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_13" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_12" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_11" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_10" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_9" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_8" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_7" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_6" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_5" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_4" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_3" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_2" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_1" BEL "u_FlashToUDP/u_scController/scRXqueue/error_IP_0" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_30" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_29" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_28" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_27" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_26" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_25" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_24" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_23" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_22" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_21" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_20" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_19" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_18" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_17" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_16" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_15" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_14" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_13" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_12" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_11" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_10" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_9" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_8" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_7" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_6" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_5" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_4" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_3" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_2" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_1" BEL "u_FlashToUDP/u_scController/scRXqueue/error_reqId_0" BEL "u_FlashToUDP/u_scController/scRXqueue/lengthAck2_i" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_31" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_30" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_29" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_28" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_27" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_26" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_25" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_24" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_23" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_22" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_21" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_20" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_19" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_18" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_17" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_16" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_15" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_14" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_13" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_12" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_11" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/srcIP_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_15" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_14" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_13" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_12" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_11" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/srcport_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/error_7" BEL "u_FlashToUDP/u_scController/scRXqueue/error_6" BEL "u_FlashToUDP/u_scController/scRXqueue/error_5" BEL "u_FlashToUDP/u_scController/scRXqueue/error_4" BEL "u_FlashToUDP/u_scController/scRXqueue/error_3" BEL "u_FlashToUDP/u_scController/scRXqueue/error_2" BEL "u_FlashToUDP/u_scController/scRXqueue/lengthAck1_i" BEL "u_FlashToUDP/u_scController/scRXqueue/portAck1_i" BEL "u_FlashToUDP/u_scController/scRXqueue/portAck_i" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_30" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_29" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_28" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_27" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_26" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_25" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_24" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_23" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_22" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_21" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_20" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_19" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_18" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_17" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_16" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_15" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_14" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_13" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_12" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_11" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/reqId_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_15" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_14" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_13" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_12" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_11" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dstport_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_15" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_14" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_13" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_12" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_11" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/length_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/rxdatavalid_q" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_4" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_5" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_6" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_7" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_8" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_9" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.gwdc0.wdc/wr_data_count_i_10" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_4" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_5" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_6" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_7" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_8" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_9" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/grstd1.grst_full.rst_d3" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/RST_FULL_GEN" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/Mshreg_txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/state_FSM_FFd1" BEL "u_FlashToUDP/u_scController/scRplyQueue/state_FSM_FFd2" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_15" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_14" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_13" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/txcounter_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_15" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_14" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_13" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/txlength_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/df_rd_en" BEL "u_FlashToUDP/u_scController/scRplyQueue/txdone" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_15" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_14" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_13" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/txframe_length_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/pf_empty_q" BEL "u_FlashToUDP/u_scController/scRplyQueue/txstart" BEL "u_FlashToUDP/u_scController/scRplyQueue/pf_rd_en" BEL "u_FlashToUDP/u_scController/scRplyQueue/txreq" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/rpkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_10" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_11" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_12" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/Mshreg_txdstrdy_q_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/rstn_synch[0]_dff_4_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/Mshreg_rstn_synch[0]_dff_4_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/state_FSM_FFd1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/state_FSM_FFd2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txcounter_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txcounter_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txcounter_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txcounter_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_7" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_6" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_5" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdata_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txreq" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/fifo_empty_q" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/fifo_rd_en" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txstart" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/txdone" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_3" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_4" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_5" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_6" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_7" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_8" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_9" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_10" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_11" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_12" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_13" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_14" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_15" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_16" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_17" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_18" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_19" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_20" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_21" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_22" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_23" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_24" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_25" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_26" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_27" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_28" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_29" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_30" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_31" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_32" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_33" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_34" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_35" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_36" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_37" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_38" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/dout_i_39" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_FlashToUDP/u_scController/scDecodeErrorQueue/scerrorFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_dcs_cmddis/st_FSM_FFd2" BEL "u_dcs_cmddis/st_FSM_FFd3" BEL "u_dcs_cmddis/st_FSM_FFd1" BEL "u_dcs_cmddis/st_FSM_FFd5" BEL "u_dcs_cmddis/st_FSM_FFd4" BEL "u_dcs_cmddis/dcs_rx_dv_40" BEL "u_dcs_cmddis/dcs_rx_dv_39" BEL "u_dcs_cmddis/dcs_rx_dv_38" BEL "u_dcs_cmddis/dcs_rx_dv_37" BEL "u_dcs_cmddis/dcs_rx_dv_36" BEL "u_dcs_cmddis/dcs_rx_dv_35" BEL "u_dcs_cmddis/dcs_rx_dv_34" BEL "u_dcs_cmddis/dcs_rx_dv_33" BEL "u_dcs_cmddis/dcs_rx_dv_32" BEL "u_dcs_cmddis/dcs_rx_dv_31" BEL "u_dcs_cmddis/dcs_rx_dv_30" BEL "u_dcs_cmddis/dcs_rx_dv_29" BEL "u_dcs_cmddis/dcs_rx_dv_28" BEL "u_dcs_cmddis/dcs_rx_dv_27" BEL "u_dcs_cmddis/dcs_rx_dv_26" BEL "u_dcs_cmddis/dcs_rx_dv_25" BEL "u_dcs_cmddis/dcs_rx_dv_24" BEL "u_dcs_cmddis/dcs_rx_dv_23" BEL "u_dcs_cmddis/dcs_rx_dv_22" BEL "u_dcs_cmddis/dcs_rx_dv_21" BEL "u_dcs_cmddis/dcs_rx_dv_20" BEL "u_dcs_cmddis/dcs_rx_dv_19" BEL "u_dcs_cmddis/dcs_rx_dv_18" BEL "u_dcs_cmddis/dcs_rx_dv_17" BEL "u_dcs_cmddis/dcs_rx_dv_16" BEL "u_dcs_cmddis/dcs_rx_dv_15" BEL "u_dcs_cmddis/dcs_rx_dv_14" BEL "u_dcs_cmddis/dcs_rx_dv_13" BEL "u_dcs_cmddis/dcs_rx_dv_12" BEL "u_dcs_cmddis/dcs_rx_dv_11" BEL "u_dcs_cmddis/dcs_rx_dv_10" BEL "u_dcs_cmddis/dcs_rx_dv_9" BEL "u_dcs_cmddis/dcs_rx_dv_8" BEL "u_dcs_cmddis/dcs_rx_dv_7" BEL "u_dcs_cmddis/dcs_rx_dv_6" BEL "u_dcs_cmddis/dcs_rx_dv_5" BEL "u_dcs_cmddis/dcs_rx_dv_4" BEL "u_dcs_cmddis/dcs_rx_dv_3" BEL "u_dcs_cmddis/dcs_rx_dv_2" BEL "u_dcs_cmddis/dcs_rx_dv_1" BEL "u_dcs_cmddis/dcs_rx_dv_0" BEL "u_dcs_cmddis/dcs_rx_dv_i_0" BEL "u_dcs_cmddis/dcs_rx_dv_i_1" BEL "u_dcs_cmddis/dcs_rx_dv_i_2" BEL "u_dcs_cmddis/dcs_rx_dv_i_3" BEL "u_dcs_cmddis/dcs_rx_dv_i_4" BEL "u_dcs_cmddis/dcs_rx_dv_i_5" BEL "u_dcs_cmddis/dcs_rx_dv_i_7" BEL "u_dcs_cmddis/dcs_rx_dv_i_6" BEL "u_dcs_cmddis/dcs_rx_dv_i_8" BEL "u_dcs_cmddis/dcs_rx_dv_i_9" BEL "u_dcs_cmddis/dcs_rx_dv_i_10" BEL "u_dcs_cmddis/dcs_rx_dv_i_11" BEL "u_dcs_cmddis/dcs_rx_dv_i_12" BEL "u_dcs_cmddis/dcs_rx_dv_i_13" BEL "u_dcs_cmddis/dcs_rx_dv_i_14" BEL "u_dcs_cmddis/dcs_rx_dv_i_15" BEL "u_dcs_cmddis/dcs_rx_dv_i_20" BEL "u_dcs_cmddis/dcs_rx_dv_i_21" BEL "u_dcs_cmddis/dcs_rx_dv_i_22" BEL "u_dcs_cmddis/dcs_rx_dv_i_23" BEL "u_dcs_cmddis/dcs_rx_dv_i_25" BEL "u_dcs_cmddis/dcs_rx_dv_i_26" BEL "u_dcs_cmddis/dcs_rx_dv_i_24" BEL "u_dcs_cmddis/dcs_rx_dv_i_27" BEL "u_dcs_cmddis/dcs_rx_dv_i_16" BEL "u_dcs_cmddis/dcs_rx_dv_i_17" BEL "u_dcs_cmddis/dcs_rx_dv_i_18" BEL "u_dcs_cmddis/dcs_rx_dv_i_19" BEL "u_dcs_cmddis/dcs_rx_dv_i_28" BEL "u_dcs_cmddis/dcs_rx_dv_i_29" BEL "u_dcs_cmddis/dcs_rx_dv_i_30" BEL "u_dcs_cmddis/dcs_rx_dv_i_31" BEL "u_dcs_cmddis/dcs_rx_dv_i_32" BEL "u_dcs_cmddis/dcs_rx_dv_i_34" BEL "u_dcs_cmddis/dcs_rx_dv_i_35" BEL "u_dcs_cmddis/dcs_rx_dv_i_33" BEL "u_dcs_cmddis/dcs_rx_dv_i_36" BEL "u_dcs_cmddis/dcs_rx_dv_i_37" BEL "u_dcs_cmddis/dcs_rx_dv_i_38" BEL "u_dcs_cmddis/dcs_rx_dv_i_39" BEL "u_dcs_cmddis/dcs_rx_dv_i_40" BEL "u_dcs_cmddis/udp_rx_src_port_0" BEL "u_dcs_cmddis/udp_rx_src_port_1" BEL "u_dcs_cmddis/udp_rx_src_port_2" BEL "u_dcs_cmddis/udp_rx_src_port_4" BEL "u_dcs_cmddis/udp_rx_src_port_5" BEL "u_dcs_cmddis/udp_rx_src_port_3" BEL "u_dcs_cmddis/udp_rx_src_port_6" BEL "u_dcs_cmddis/udp_rx_src_port_7" BEL "u_dcs_cmddis/udp_rx_dst_port_0" BEL "u_dcs_cmddis/udp_rx_dst_port_1" BEL "u_dcs_cmddis/udp_rx_dst_port_2" BEL "u_dcs_cmddis/udp_rx_dst_port_3" BEL "u_dcs_cmddis/udp_rx_dst_port_5" BEL "u_dcs_cmddis/udp_rx_dst_port_6" BEL "u_dcs_cmddis/udp_rx_dst_port_4" BEL "u_dcs_cmddis/udp_rx_dst_port_7" BEL "u_dcs_cmddis/udp_rx_src_port_8" BEL "u_dcs_cmddis/udp_rx_src_port_9" BEL "u_dcs_cmddis/udp_rx_src_port_10" BEL "u_dcs_cmddis/udp_rx_src_port_11" BEL "u_dcs_cmddis/udp_rx_src_port_12" BEL "u_dcs_cmddis/udp_rx_src_port_13" BEL "u_dcs_cmddis/udp_rx_src_port_14" BEL "u_dcs_cmddis/udp_rx_src_port_15" BEL "u_dcs_cmddis/udp_rx_dst_port_8" BEL "u_dcs_cmddis/udp_rx_dst_port_9" BEL "u_dcs_cmddis/udp_rx_dst_port_10" BEL "u_dcs_cmddis/udp_rx_dst_port_11" BEL "u_dcs_cmddis/udp_rx_dst_port_12" BEL "u_dcs_cmddis/udp_rx_dst_port_14" BEL "u_dcs_cmddis/udp_rx_dst_port_15" BEL "u_dcs_cmddis/udp_rx_dst_port_13" BEL "u_dcs_cmddis/dcs_rxd_7" BEL "u_dcs_cmddis/dcs_rxd_6" BEL "u_dcs_cmddis/dcs_rxd_5" BEL "u_dcs_cmddis/dcs_rxd_4" BEL "u_dcs_cmddis/dcs_rxd_3" BEL "u_dcs_cmddis/dcs_rxd_2" BEL "u_dcs_cmddis/dcs_rxd_1" BEL "u_dcs_cmddis/dcs_rxd_0" BEL "u_dcs_cmddis/synch_udprx/o" BEL "u_dcs_cmddis/synch_udprx/Mshreg_o" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM1_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM10_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM100_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM100_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM100_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM100_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM101_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM101_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM101_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM101_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM102_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM102_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM102_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM102_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM103_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM103_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM103_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM103_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM104_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM104_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM104_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM104_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM105_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM105_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM105_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM105_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM106_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM106_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM106_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM106_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM107_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM107_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM107_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM107_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM108_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM108_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM108_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM108_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM109_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM109_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM109_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM109_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM11_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM110_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM110_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM110_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM110_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM111_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM111_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM111_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM111_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM112_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM112_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM112_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM112_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM113_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM113_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM113_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM113_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM114_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM114_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM114_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM114_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM115_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM115_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM115_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM115_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM116_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM116_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM116_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM116_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM117_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM117_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM117_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM117_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM118_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM118_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM118_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM118_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM119_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM119_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM119_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM119_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM12_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM120_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM120_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM120_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM120_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM121_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM121_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM121_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM121_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM122_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM122_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM122_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM122_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM123_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM123_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM123_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM123_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM124_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM124_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM124_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM124_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM125_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM125_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM125_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM125_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM126_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM126_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM126_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM126_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM127_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM127_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM127_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM127_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM128_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM128_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM128_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM128_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM129_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM129_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM129_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM129_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM13_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM130_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM130_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM130_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM130_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM131_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM131_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM131_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM131_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM132_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM132_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM132_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM132_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM133_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM133_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM133_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM133_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM134_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM134_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM134_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM134_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM135_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM135_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM135_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM135_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM136_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM136_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM136_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM136_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM137_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM137_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM137_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM137_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM138_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM138_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM138_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM138_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM139_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM139_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM139_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM139_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM14_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM140_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM140_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM140_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM140_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM141_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM141_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM141_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM141_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM142_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM142_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM142_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM142_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM143_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM143_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM143_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM143_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM144_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM144_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM144_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM144_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM145_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM145_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM145_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM145_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM146_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM146_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM146_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM146_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM147_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM147_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM147_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM147_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM148_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM148_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM148_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM148_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM149_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM149_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM149_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM149_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM15_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM150_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM150_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM150_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM150_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM151_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM151_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM151_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM151_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM152_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM152_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM152_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM152_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM153_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM153_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM153_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM153_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM154_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM154_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM154_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM154_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM155_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM155_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM155_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM155_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM156_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM156_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM156_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM156_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM157_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM157_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM157_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM157_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM158_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM158_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM158_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM158_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM159_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM159_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM159_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM159_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM16_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM160_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM160_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM160_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM160_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM161_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM161_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM161_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM161_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM162_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM162_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM162_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM162_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM163_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM163_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM163_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM163_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM164_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM164_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM164_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM164_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM165_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM165_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM165_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM165_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM166_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM166_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM166_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM166_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM167_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM167_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM167_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM167_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM168_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM168_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM168_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM168_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM169_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM169_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM169_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM169_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM17_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM170_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM170_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM170_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM170_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM171_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM171_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM171_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM171_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM172_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM172_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM172_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM172_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM173_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM173_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM173_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM173_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM174_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM174_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM174_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM174_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM175_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM175_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM175_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM175_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM176_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM176_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM176_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM176_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM177_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM177_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM177_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM177_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM178_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM178_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM178_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM178_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM179_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM179_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM179_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM179_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM18_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM180_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM180_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM180_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM180_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM181_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM181_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM181_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM181_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM182_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM182_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM182_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM182_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM183_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM183_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM183_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM183_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM184_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM184_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM184_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM184_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM185_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM185_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM185_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM185_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM186_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM186_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM186_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM186_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM187_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM187_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM187_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM187_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM188_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM188_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM188_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM188_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM189_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM189_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM189_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM189_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM19_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM190_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM190_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM190_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM190_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM191_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM191_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM191_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM191_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM192_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM192_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM192_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM192_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM2_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM20_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM21_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM22_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM23_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM24_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM25_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM26_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM27_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM28_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM29_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM3_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM30_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM31_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM32_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM33_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM34_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM35_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM36_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM37_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM38_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM39_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM4_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM40_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM41_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM42_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM43_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM44_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM45_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM46_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM47_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM48_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM49_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM5_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM50_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM51_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM52_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM53_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM54_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM55_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM56_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM57_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM58_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM59_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM6_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM60_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM61_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM62_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM63_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM64_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM7_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM8_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM81_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM82_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM83_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM84_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM85_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM86_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM87_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM88_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM89_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM9_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM90_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM91_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM92_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM93_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM94_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM95_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM96_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM97_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM97_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM97_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM97_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM98_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM98_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM98_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM98_RAMD" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM99_RAMA" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM99_RAMB" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM99_RAMC" BEL "u_FlashToUDP/u_scController/scRXqueue/pkgFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM99_RAMD" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<32>" PIN "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_FlashToUDP/u_scController/scRXqueue/dataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_FlashToUDP/u_scController/scRplyQueue/rdataFIFO/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_sru_dcscmd_par/u_fifo_8to32b/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<63>" PIN "u_sru_trigger/u_event_number_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.WIDE_PRIM36.ram_pins<62>" PIN "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_FlashToUDP/u_UDPSCConv/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<63>" PIN "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<62>" PIN "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<65>" PIN "u_dcs_eth_top/u_Eth_tx_fsm/Eth_tx_tx_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_dcs_eth_top/u_arp_reply_fsm/arp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_dcs_eth_top/u_ip_packet_proc_fsm/icmp_tx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_dcs_eth_top/u_ip_reply_fsm/ip_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<63>" PIN "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<62>" PIN "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<65>" PIN "u_dcs_eth_top/u_rx_ip_fsm_fifo_8/tx_fifo_i/ramgen_pins<64>" PIN "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_dcs_eth_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<63>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<62>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<65>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/ramgen_pins<64>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<63>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<62>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<65>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<63>" PIN "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<62>" PIN "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_40dtc_top/u_udp_reply_mux/udp_reply_tx_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<65>" PIN "u_sru_cmd_par/u_sru_dcs_fifo/u_dcs_client_fifo_wr_fsm/u_rx_client_fifo_8_rdbus/u_rx_client_fifo_8_f1/ramgen_pins<64>"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout2 = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout3_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout2_0 = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout3_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout2_1 = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout3_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout2_2 = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout3_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout2_3 = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_serclkdiv/o" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/synch_serclkdiv/Mshreg_o" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd8" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd10" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd11" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd13" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd14" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/st_FSM_FFd12" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/cmd_dv_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/rdocmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_7" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_6" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_5" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_4" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_3" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/dtc_pdin_0" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/abortcmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/FastCmd_ack" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_FastCmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_abortcmd/cmd_buffer" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd1" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/st_FSM_FFd2" BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx/u_rdocmd/cmd_buffer" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout3_buf"; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave" PINNAME CLKB; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLK; PIN u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4> = BEL "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master" PINNAME CLKB; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout4 = PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout5_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout4_0 = PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout5_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout4_1 = PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout5_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout4_2 = PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout5_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout4_3 = PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[39].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[38].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[37].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[36].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[35].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[34].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[33].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[32].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[31].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[30].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[29].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[28].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[27].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[26].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[25].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[24].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[23].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[22].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[21].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[20].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[19].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[18].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[17].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[16].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[15].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[14].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[13].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[12].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[11].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[10].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[9].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[8].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[7].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[6].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[5].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[4].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[3].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[2].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[1].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_slave_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<3>" PIN "u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser/u_dtc_deser_f/pins[0].iserdese1_master_pins<4>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout5_buf"; PIN u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<151> = BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i" PINNAME RXUSRCLK2; PIN u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<289> = BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i" PINNAME TXUSRCLK2; PIN u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<18> = BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac" PINNAME CLIENTEMACRXCLIENTCLKIN; PIN u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<19> = BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac" PINNAME CLIENTEMACTXCLIENTCLKIN; PIN u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<172> = BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac" PINNAME PHYEMACGTXCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram" PINNAME CLKBWRCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<32> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram" PINNAME CLKARDCLK; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKARDCLKL; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKU; PIN u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64> = BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram" PINNAME CLKBWRCLKL; TIMEGRP sfpClkOut = BEL "u_sru_40dtc_top/u_dtc_multiram/last_packet_toggle" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_31" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_30" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_29" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_28" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_27" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_26" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_25" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_24" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_23" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_22" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_21" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_20" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_19" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_18" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_17" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_16" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_15" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_14" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_13" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_12" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_11" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_10" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_9" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_8" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/holding_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/fifo_empty_1_d" BEL "u_sru_40dtc_top/u_dtc_multiram/fifo_empty_0_d" BEL "u_sru_40dtc_top/u_dtc_multiram/state_1" BEL "u_sru_40dtc_top/u_dtc_multiram/state_0" BEL "u_sru_40dtc_top/u_dtc_multiram/inject_DTC_link_ID_d" BEL "u_sru_40dtc_top/u_dtc_multiram/packet_fifo_wen_d" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_b/o" BEL "u_sru_40dtc_top/u_dtc_multiram/sync_b/Mshreg_o" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/out2_wg_cy_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_out2_wg_cy_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_39" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_39" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_37" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_37" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_36" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_36" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_38" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_38" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_35" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_35" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_34" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_34" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_31" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_31" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_33" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_33" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_30" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_30" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_29" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_29" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_27" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_27" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_26" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_26" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_28" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_28" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_25" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_25" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_24" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_24" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_22" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_22" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_21" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_21" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_23" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_23" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_20" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_20" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_19" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_19" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_17" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_17" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_16" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_16" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_18" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_18" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_15" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_15" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_14" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_14" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DTCEventRdy_dd_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/Mshreg_DTCEventRdy_dd_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/size_wr_en" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/cnt_ram_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_10_BRB3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_10_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_9_BRB3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_9_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_8_BRB3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_8_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_7_BRB3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_7_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_6_BRB3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_6_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_5_BRB3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_5_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_4_BRB3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_4_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_3_BRB3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_3_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_3_BRB0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_15_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_14_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_13_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_12_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_11_BRB1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_11_BRB0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/wait_cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/wait_cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/wait_cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/wait_cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/wait_cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/wait_cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/state_FSM_FFd5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/state_FSM_FFd6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/state_FSM_FFd4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/state_FSM_FFd7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/index_1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/index_1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/index_1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/index_1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/index_1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/index_1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/index_0_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/index_0_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/index_0_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/index_0_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/index_0_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_15" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_14" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_39" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_38" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_37" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_36" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_35" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_34" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_33" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_31" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_30" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_29" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_28" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_27" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_26" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_25" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_24" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_23" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_22" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_21" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_20" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_19" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_18" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_17" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_16" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_15" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_14" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/DtcRamReadConfirm_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_size_i_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_i_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_i_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_i_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_i_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_i_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_i_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_i_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_i_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_i_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/channels_in_packet_i_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_15" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_14" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_addr_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_39" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_38" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_37" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_36" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_35" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_34" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_33" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_31" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_30" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_29" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_28" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_27" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_26" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_25" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_24" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_23" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_22" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_21" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_20" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_19" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_18" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_17" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_16" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_15" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_14" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fec_read_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/inject_DTC_link_ID" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/last_packet" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/packet_fifo_wen" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/fifo_ren" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ch_size_d_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ch_size_d_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ch_size_d_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ch_size_d_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ch_size_d_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ch_size_d_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ch_size_d_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ch_size_d_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ch_size_d_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/ram_rd_cnt_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/picked_ram_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/picked_ram_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/picked_ram_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/picked_ram_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/picked_ram_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/picked_ram_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_packet_lenght_fsm/UDP_transfer_active" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_14" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_15" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_16" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_17" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_18" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_19" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_20" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_21" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_22" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_23" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_24" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_25" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_26" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_27" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_28" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_29" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_30" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_31" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/sel_pipe_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_14" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_15" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_16" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_17" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_18" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_19" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_20" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_21" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_22" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_23" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_24" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_25" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_26" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_27" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_28" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_29" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_30" BEL "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/dout_i_31" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_bin_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_bin_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d1_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d2_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d2_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d2_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d2_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d2_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d2_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d2_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d2_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d2_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d2_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_almost_full_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/crd/count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c1/count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/c0/count_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/wsts/ram_full_fb_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl1.lsshft/rsts/ram_empty_fb_i" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_3" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_4" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_5" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_6" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_7" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_8" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_9" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_10" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_11" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_12" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_13" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_14" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_15" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_16" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_17" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_18" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_19" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_20" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_21" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_22" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_23" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_24" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_25" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/dout_i_26" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg" BEL "u_udp_mac/synch_sfp/o" BEL "u_udp_mac/synch_sfp/Mshreg_o" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/ip_tx_start_reg" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/udp_tx_state_FSM_FFd1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/udp_tx_state_FSM_FFd2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_15" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_14" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_13" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_12" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_11" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/udp_tx_block/tx_count_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/mac_lookup_req" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_15" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_14" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_13" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_12" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_11" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_count_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_state_FSM_FFd1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_state_FSM_FFd2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_state_FSM_FFd3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/crc_state_FSM_FFd1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/crc_state_FSM_FFd2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/crc_state_FSM_FFd4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/crc_state_FSM_FFd3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_chn_reqd" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_47" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_46" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_45" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_44" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_43" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_42" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_41" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_40" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_39" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_38" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_37" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_36" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_35" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_34" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_33" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_32" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_31" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_30" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_29" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_28" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_27" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_26" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_25" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_24" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_23" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_22" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_21" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_20" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_19" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_18" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_17" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_16" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_15" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_14" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_13" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_12" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_11" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_mac_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_result_reg_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_result_reg_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_23" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_22" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_21" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_20" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_19" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_18" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_17" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_16" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_15" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_14" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_13" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_12" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_11" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/tx_hdr_cks_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_31" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_30" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_29" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_28" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_27" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_26" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_25" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_24" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_23" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_22" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_21" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_20" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_19" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_18" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_17" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_16" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_15" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_14" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_13" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_12" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_11" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/IP_layer/TX/arp_req_ip_reg_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_mac_chn_reqd" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timeout_reg" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_reply_required" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_31_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_30_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_29_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_28_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_27_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_26_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_25_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_24_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_24_BRB0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_23_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_22_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_21_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_20_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_19_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_18_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_17_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_16_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_16_BRB0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_15_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_14_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_13_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_12_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_11_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_10_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_9_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_8_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_8_BRB0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_7_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_6_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_5_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_4_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_3_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_2_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_1_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_0_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_0_BRB0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_31_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_30_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_29_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_28_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_27_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_26_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_25_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_24_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_24_BRB0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_23_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_22_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_21_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_20_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_19_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_18_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_17_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_16_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_16_BRB0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_15_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_14_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_13_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_12_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_11_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_10_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_9_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_8_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_8_BRB0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_7_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_7_BRB1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_6_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_6_BRB1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_5_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_5_BRB1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_4_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_4_BRB1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_3_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_3_BRB1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_2_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_2_BRB1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_1_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_1_BRB1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_0_BRB3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_0_BRB2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_0_BRB1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_ip_0_BRB0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_valid_reg" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/send_request_needed" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_is_valid" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_count_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_state_FSM_FFd1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_state_FSM_FFd1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_state_FSM_FFd2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/rx_state_FSM_FFd2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_state_FSM_FFd3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_count_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_count_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_count_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_count_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_count_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_count_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_count_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_count_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_state_FSM_FFd1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/tx_state_FSM_FFd2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/timer_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_47" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_46" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_45" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_44" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_43" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_42" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_41" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_40" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_39" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_38" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_37" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_36" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_35" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_34" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_33" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_32" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_31" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_30" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_29" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_28" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_27" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_26" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_25" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_24" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_23" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_22" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_21" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_20" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_19" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_18" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_17" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_16" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_15" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_14" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_13" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_12" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_11" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/mac_addr_found_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_47" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_46" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_45" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_44" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_43" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_42" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_41" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_40" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_39" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_38" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_37" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_36" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_35" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_34" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_33" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_32" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_31" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_30" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_29" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_28" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_27" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_26" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_25" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_24" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_23" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_22" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_21" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_20" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_19" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_18" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_17" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_16" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_15" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_14" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_13" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_12" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_11" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_mac_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_31" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_30" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_29" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_28" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_27" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_26" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_25" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_24" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_23" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_22" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_21" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_20" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_19" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_18" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_17" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_16" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_15" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_14" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_13" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_12" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_11" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_entry_ip_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_47" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_46" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_45" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_44" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_43" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_42" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_41" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_40" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_39" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_38" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_37" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_36" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_35" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_34" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_33" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/new_arp_entry_mac_32" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_operation_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/arp_operation_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_26" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_25" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_24" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_23" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_22" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_21" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_20" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_19" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_18" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_17" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_16" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_15" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_14" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_13" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_12" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_11" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/freq_scaler_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_31" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_30" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_29" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_28" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_27" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_26" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_25" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_24" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_23" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_22" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_21" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_20" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_19" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_18" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_17" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_16" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_15" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_14" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_13" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_12" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_11" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/signle_entry_arp.arp_layer/req_ip_addr_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/udp_block/IP_block/mac_tx_arb/grant" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rxrundisp_r" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rxnotintable_r" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rxdisperr_r" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gmii_rxd_int_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gmii_rxd_int_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gmii_rxd_int_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gmii_rxd_int_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gmii_rxd_int_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gmii_rxd_int_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gmii_rxd_int_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gmii_rxd_int_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rxclkcorcnt_r_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rxclkcorcnt_r_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rxclkcorcnt_r_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rxcharisk_r" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/rxchariscomma_r" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/mgt_tx_data_r_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/mgt_tx_data_r_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/mgt_tx_data_r_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/mgt_tx_data_r_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/mgt_tx_data_r_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/mgt_tx_data_r_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/mgt_tx_data_r_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/mgt_tx_data_r_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/txcharisk_r" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/txchardispval_r" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/txchardispmode_r" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gtx_pre_resetn" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gtx_resetn" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<151>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<289>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<151>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<289>" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gtx_reset_gen/reset_sync2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/gtx_reset_gen/reset_sync1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/SYNC_TX_RESET_I/R3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/SYNC_TX_RESET_I/R4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/SYNC_RX_RESET_I/R3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/SYNC_RX_RESET_I/R4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_frame_complete" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/force_end" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_state_FSM_FFd1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/no_burst" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/two_byte_tx" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_underrun" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tlast_reg" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/ignore_packet" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_valid" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/early_underrun" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/early_deassert" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/force_burst1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/force_assert" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/force_burst2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_data_reg_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_data_reg_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_data_reg_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_data_reg_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_data_reg_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_data_reg_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_data_reg_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_data_reg_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_mac_tvalid" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_mac_tlast" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_mac_tdata_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_mac_tdata_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_mac_tdata_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_mac_tdata_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_mac_tdata_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_mac_tdata_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_mac_tdata_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_mac_tdata_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/rx_axi_shim/rx_state_FSM_FFd2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_mac_tready_reg" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_hold_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_data_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/tx_axi_shim/tx_state_FSM_FFd2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/SYNC_TX_RESET_I/R2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/SYNC_TX_RESET_I/R1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/SYNC_RX_RESET_I/R2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/SYNC_RX_RESET_I/R1" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<18>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<19>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<172>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<18>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<19>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<172>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<18>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<19>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6emac_core/BU2/U0/v6_emac_pins<172>" BEL "u_udp_mac/u_udp_fsm/event_number_fifo_rd_en" BEL "u_udp_mac/u_udp_fsm/Result<9>1_FRB" BEL "u_udp_mac/u_udp_fsm/Result<8>1_FRB" BEL "u_udp_mac/u_udp_fsm/Result<7>1_FRB" BEL "u_udp_mac/u_udp_fsm/Result<6>1_FRB" BEL "u_udp_mac/u_udp_fsm/Result<5>2_FRB" BEL "u_udp_mac/u_udp_fsm/Result<4>2_FRB" BEL "u_udp_mac/u_udp_fsm/Result<3>2_FRB" BEL "u_udp_mac/u_udp_fsm/Result<2>2_FRB" BEL "u_udp_mac/u_udp_fsm/Result<1>2_FRB" BEL "u_udp_mac/u_udp_fsm/Result<0>2_FRB" BEL "u_udp_mac/u_udp_fsm/Result<15>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<14>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<13>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<12>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<11>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<10>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<9>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<8>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<7>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<6>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<5>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<4>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<3>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<2>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<1>_FRB" BEL "u_udp_mac/u_udp_fsm/Result<0>_FRB" BEL "u_udp_mac/u_udp_fsm/current_packet_count_9" BEL "u_udp_mac/u_udp_fsm/current_packet_count_8" BEL "u_udp_mac/u_udp_fsm/current_packet_count_7" BEL "u_udp_mac/u_udp_fsm/current_packet_count_6" BEL "u_udp_mac/u_udp_fsm/current_packet_count_5" BEL "u_udp_mac/u_udp_fsm/current_packet_count_4" BEL "u_udp_mac/u_udp_fsm/current_packet_count_3" BEL "u_udp_mac/u_udp_fsm/current_packet_count_2" BEL "u_udp_mac/u_udp_fsm/current_packet_count_1" BEL "u_udp_mac/u_udp_fsm/current_packet_count_0" BEL "u_udp_mac/u_udp_fsm/running_packet_count_5" BEL "u_udp_mac/u_udp_fsm/running_packet_count_4" BEL "u_udp_mac/u_udp_fsm/running_packet_count_3" BEL "u_udp_mac/u_udp_fsm/running_packet_count_2" BEL "u_udp_mac/u_udp_fsm/running_packet_count_1" BEL "u_udp_mac/u_udp_fsm/running_packet_count_0" BEL "u_udp_mac/u_udp_fsm/byte_counter_15" BEL "u_udp_mac/u_udp_fsm/byte_counter_14" BEL "u_udp_mac/u_udp_fsm/byte_counter_13" BEL "u_udp_mac/u_udp_fsm/byte_counter_12" BEL "u_udp_mac/u_udp_fsm/byte_counter_11" BEL "u_udp_mac/u_udp_fsm/byte_counter_10" BEL "u_udp_mac/u_udp_fsm/byte_counter_9" BEL "u_udp_mac/u_udp_fsm/byte_counter_8" BEL "u_udp_mac/u_udp_fsm/byte_counter_7" BEL "u_udp_mac/u_udp_fsm/byte_counter_6" BEL "u_udp_mac/u_udp_fsm/byte_counter_5" BEL "u_udp_mac/u_udp_fsm/byte_counter_4" BEL "u_udp_mac/u_udp_fsm/byte_counter_3" BEL "u_udp_mac/u_udp_fsm/byte_counter_2" BEL "u_udp_mac/u_udp_fsm/byte_counter_1" BEL "u_udp_mac/u_udp_fsm/byte_counter_0" BEL "u_udp_mac/u_udp_fsm/state_FSM_FFd1" BEL "u_udp_mac/u_udp_fsm/state_FSM_FFd2" BEL "u_udp_mac/u_udp_fsm/state_FSM_FFd3" BEL "u_udp_mac/u_udp_fsm/state_FSM_FFd4" BEL "u_udp_mac/u_udp_fsm/state_FSM_FFd5" BEL "u_udp_mac/u_udp_fsm/packet_trace_255" BEL "u_udp_mac/u_udp_fsm/packet_trace_254" BEL "u_udp_mac/u_udp_fsm/packet_trace_253" BEL "u_udp_mac/u_udp_fsm/packet_trace_252" BEL "u_udp_mac/u_udp_fsm/packet_trace_251" BEL "u_udp_mac/u_udp_fsm/packet_trace_250" BEL "u_udp_mac/u_udp_fsm/packet_trace_249" BEL "u_udp_mac/u_udp_fsm/packet_trace_248" BEL "u_udp_mac/u_udp_fsm/packet_trace_247" BEL "u_udp_mac/u_udp_fsm/packet_trace_246" BEL "u_udp_mac/u_udp_fsm/packet_trace_245" BEL "u_udp_mac/u_udp_fsm/packet_trace_244" BEL "u_udp_mac/u_udp_fsm/packet_trace_243" BEL "u_udp_mac/u_udp_fsm/packet_trace_242" BEL "u_udp_mac/u_udp_fsm/packet_trace_241" BEL "u_udp_mac/u_udp_fsm/packet_trace_240" BEL "u_udp_mac/u_udp_fsm/packet_trace_239" BEL "u_udp_mac/u_udp_fsm/packet_trace_238" BEL "u_udp_mac/u_udp_fsm/packet_trace_237" BEL "u_udp_mac/u_udp_fsm/packet_trace_236" BEL "u_udp_mac/u_udp_fsm/packet_trace_235" BEL "u_udp_mac/u_udp_fsm/packet_trace_234" BEL "u_udp_mac/u_udp_fsm/packet_trace_233" BEL "u_udp_mac/u_udp_fsm/packet_trace_232" BEL "u_udp_mac/u_udp_fsm/packet_trace_229" BEL "u_udp_mac/u_udp_fsm/packet_trace_228" BEL "u_udp_mac/u_udp_fsm/packet_trace_227" BEL "u_udp_mac/u_udp_fsm/packet_trace_226" BEL "u_udp_mac/u_udp_fsm/packet_trace_225" BEL "u_udp_mac/u_udp_fsm/packet_trace_224" BEL "u_udp_mac/u_udp_fsm/packet_trace_223" BEL "u_udp_mac/u_udp_fsm/packet_trace_222" BEL "u_udp_mac/u_udp_fsm/packet_trace_221" BEL "u_udp_mac/u_udp_fsm/packet_trace_220" BEL "u_udp_mac/u_udp_fsm/packet_trace_219" BEL "u_udp_mac/u_udp_fsm/packet_trace_218" BEL "u_udp_mac/u_udp_fsm/packet_trace_217" BEL "u_udp_mac/u_udp_fsm/packet_trace_216" BEL "u_udp_mac/u_udp_fsm/packet_trace_215" BEL "u_udp_mac/u_udp_fsm/packet_trace_214" BEL "u_udp_mac/u_udp_fsm/packet_trace_213" BEL "u_udp_mac/u_udp_fsm/packet_trace_212" BEL "u_udp_mac/u_udp_fsm/packet_trace_211" BEL "u_udp_mac/u_udp_fsm/packet_trace_210" BEL "u_udp_mac/u_udp_fsm/packet_trace_209" BEL "u_udp_mac/u_udp_fsm/packet_trace_208" BEL "u_udp_mac/u_udp_fsm/packet_trace_207" BEL "u_udp_mac/u_udp_fsm/packet_trace_206" BEL "u_udp_mac/u_udp_fsm/packet_trace_205" BEL "u_udp_mac/u_udp_fsm/packet_trace_204" BEL "u_udp_mac/u_udp_fsm/packet_trace_203" BEL "u_udp_mac/u_udp_fsm/packet_trace_202" BEL "u_udp_mac/u_udp_fsm/packet_trace_201" BEL "u_udp_mac/u_udp_fsm/packet_trace_200" BEL "u_udp_mac/u_udp_fsm/packet_trace_197" BEL "u_udp_mac/u_udp_fsm/packet_trace_196" BEL "u_udp_mac/u_udp_fsm/packet_trace_195" BEL "u_udp_mac/u_udp_fsm/packet_trace_194" BEL "u_udp_mac/u_udp_fsm/packet_trace_193" BEL "u_udp_mac/u_udp_fsm/packet_trace_192" BEL "u_udp_mac/u_udp_fsm/packet_trace_191" BEL "u_udp_mac/u_udp_fsm/packet_trace_190" BEL "u_udp_mac/u_udp_fsm/packet_trace_189" BEL "u_udp_mac/u_udp_fsm/packet_trace_188" BEL "u_udp_mac/u_udp_fsm/packet_trace_187" BEL "u_udp_mac/u_udp_fsm/packet_trace_186" BEL "u_udp_mac/u_udp_fsm/packet_trace_185" BEL "u_udp_mac/u_udp_fsm/packet_trace_184" BEL "u_udp_mac/u_udp_fsm/packet_trace_183" BEL "u_udp_mac/u_udp_fsm/packet_trace_182" BEL "u_udp_mac/u_udp_fsm/packet_trace_181" BEL "u_udp_mac/u_udp_fsm/packet_trace_180" BEL "u_udp_mac/u_udp_fsm/packet_trace_179" BEL "u_udp_mac/u_udp_fsm/packet_trace_178" BEL "u_udp_mac/u_udp_fsm/packet_trace_177" BEL "u_udp_mac/u_udp_fsm/packet_trace_176" BEL "u_udp_mac/u_udp_fsm/packet_trace_175" BEL "u_udp_mac/u_udp_fsm/packet_trace_174" BEL "u_udp_mac/u_udp_fsm/packet_trace_173" BEL "u_udp_mac/u_udp_fsm/packet_trace_172" BEL "u_udp_mac/u_udp_fsm/packet_trace_171" BEL "u_udp_mac/u_udp_fsm/packet_trace_170" BEL "u_udp_mac/u_udp_fsm/packet_trace_169" BEL "u_udp_mac/u_udp_fsm/packet_trace_168" BEL "u_udp_mac/u_udp_fsm/packet_trace_165" BEL "u_udp_mac/u_udp_fsm/packet_trace_164" BEL "u_udp_mac/u_udp_fsm/packet_trace_163" BEL "u_udp_mac/u_udp_fsm/packet_trace_162" BEL "u_udp_mac/u_udp_fsm/packet_trace_161" BEL "u_udp_mac/u_udp_fsm/packet_trace_160" BEL "u_udp_mac/u_udp_fsm/packet_trace_159" BEL "u_udp_mac/u_udp_fsm/packet_trace_158" BEL "u_udp_mac/u_udp_fsm/packet_trace_157" BEL "u_udp_mac/u_udp_fsm/packet_trace_156" BEL "u_udp_mac/u_udp_fsm/packet_trace_155" BEL "u_udp_mac/u_udp_fsm/packet_trace_154" BEL "u_udp_mac/u_udp_fsm/packet_trace_153" BEL "u_udp_mac/u_udp_fsm/packet_trace_152" BEL "u_udp_mac/u_udp_fsm/packet_trace_151" BEL "u_udp_mac/u_udp_fsm/packet_trace_150" BEL "u_udp_mac/u_udp_fsm/packet_trace_149" BEL "u_udp_mac/u_udp_fsm/packet_trace_148" BEL "u_udp_mac/u_udp_fsm/packet_trace_147" BEL "u_udp_mac/u_udp_fsm/packet_trace_146" BEL "u_udp_mac/u_udp_fsm/packet_trace_145" BEL "u_udp_mac/u_udp_fsm/packet_trace_144" BEL "u_udp_mac/u_udp_fsm/packet_trace_143" BEL "u_udp_mac/u_udp_fsm/packet_trace_142" BEL "u_udp_mac/u_udp_fsm/packet_trace_141" BEL "u_udp_mac/u_udp_fsm/packet_trace_140" BEL "u_udp_mac/u_udp_fsm/packet_trace_139" BEL "u_udp_mac/u_udp_fsm/packet_trace_138" BEL "u_udp_mac/u_udp_fsm/packet_trace_137" BEL "u_udp_mac/u_udp_fsm/packet_trace_136" BEL "u_udp_mac/u_udp_fsm/packet_trace_133" BEL "u_udp_mac/u_udp_fsm/packet_trace_132" BEL "u_udp_mac/u_udp_fsm/packet_trace_131" BEL "u_udp_mac/u_udp_fsm/packet_trace_130" BEL "u_udp_mac/u_udp_fsm/packet_trace_129" BEL "u_udp_mac/u_udp_fsm/packet_trace_128" BEL "u_udp_mac/u_udp_fsm/packet_trace_127" BEL "u_udp_mac/u_udp_fsm/packet_trace_126" BEL "u_udp_mac/u_udp_fsm/packet_trace_125" BEL "u_udp_mac/u_udp_fsm/packet_trace_124" BEL "u_udp_mac/u_udp_fsm/packet_trace_123" BEL "u_udp_mac/u_udp_fsm/packet_trace_122" BEL "u_udp_mac/u_udp_fsm/packet_trace_121" BEL "u_udp_mac/u_udp_fsm/packet_trace_120" BEL "u_udp_mac/u_udp_fsm/packet_trace_119" BEL "u_udp_mac/u_udp_fsm/packet_trace_118" BEL "u_udp_mac/u_udp_fsm/packet_trace_117" BEL "u_udp_mac/u_udp_fsm/packet_trace_116" BEL "u_udp_mac/u_udp_fsm/packet_trace_115" BEL "u_udp_mac/u_udp_fsm/packet_trace_114" BEL "u_udp_mac/u_udp_fsm/packet_trace_113" BEL "u_udp_mac/u_udp_fsm/packet_trace_112" BEL "u_udp_mac/u_udp_fsm/packet_trace_111" BEL "u_udp_mac/u_udp_fsm/packet_trace_110" BEL "u_udp_mac/u_udp_fsm/packet_trace_109" BEL "u_udp_mac/u_udp_fsm/packet_trace_108" BEL "u_udp_mac/u_udp_fsm/packet_trace_107" BEL "u_udp_mac/u_udp_fsm/packet_trace_106" BEL "u_udp_mac/u_udp_fsm/packet_trace_105" BEL "u_udp_mac/u_udp_fsm/packet_trace_104" BEL "u_udp_mac/u_udp_fsm/packet_trace_101" BEL "u_udp_mac/u_udp_fsm/packet_trace_100" BEL "u_udp_mac/u_udp_fsm/packet_trace_99" BEL "u_udp_mac/u_udp_fsm/packet_trace_98" BEL "u_udp_mac/u_udp_fsm/packet_trace_97" BEL "u_udp_mac/u_udp_fsm/packet_trace_96" BEL "u_udp_mac/u_udp_fsm/packet_trace_95" BEL "u_udp_mac/u_udp_fsm/packet_trace_94" BEL "u_udp_mac/u_udp_fsm/packet_trace_93" BEL "u_udp_mac/u_udp_fsm/packet_trace_92" BEL "u_udp_mac/u_udp_fsm/packet_trace_91" BEL "u_udp_mac/u_udp_fsm/packet_trace_90" BEL "u_udp_mac/u_udp_fsm/packet_trace_89" BEL "u_udp_mac/u_udp_fsm/packet_trace_88" BEL "u_udp_mac/u_udp_fsm/packet_trace_87" BEL "u_udp_mac/u_udp_fsm/packet_trace_86" BEL "u_udp_mac/u_udp_fsm/packet_trace_85" BEL "u_udp_mac/u_udp_fsm/packet_trace_84" BEL "u_udp_mac/u_udp_fsm/packet_trace_83" BEL "u_udp_mac/u_udp_fsm/packet_trace_82" BEL "u_udp_mac/u_udp_fsm/packet_trace_81" BEL "u_udp_mac/u_udp_fsm/packet_trace_80" BEL "u_udp_mac/u_udp_fsm/packet_trace_79" BEL "u_udp_mac/u_udp_fsm/packet_trace_78" BEL "u_udp_mac/u_udp_fsm/packet_trace_77" BEL "u_udp_mac/u_udp_fsm/packet_trace_76" BEL "u_udp_mac/u_udp_fsm/packet_trace_75" BEL "u_udp_mac/u_udp_fsm/packet_trace_74" BEL "u_udp_mac/u_udp_fsm/packet_trace_73" BEL "u_udp_mac/u_udp_fsm/packet_trace_72" BEL "u_udp_mac/u_udp_fsm/packet_trace_69" BEL "u_udp_mac/u_udp_fsm/packet_trace_68" BEL "u_udp_mac/u_udp_fsm/packet_trace_67" BEL "u_udp_mac/u_udp_fsm/packet_trace_66" BEL "u_udp_mac/u_udp_fsm/packet_trace_65" BEL "u_udp_mac/u_udp_fsm/packet_trace_64" BEL "u_udp_mac/u_udp_fsm/packet_trace_63" BEL "u_udp_mac/u_udp_fsm/packet_trace_62" BEL "u_udp_mac/u_udp_fsm/packet_trace_61" BEL "u_udp_mac/u_udp_fsm/packet_trace_60" BEL "u_udp_mac/u_udp_fsm/packet_trace_59" BEL "u_udp_mac/u_udp_fsm/packet_trace_58" BEL "u_udp_mac/u_udp_fsm/packet_trace_57" BEL "u_udp_mac/u_udp_fsm/packet_trace_56" BEL "u_udp_mac/u_udp_fsm/packet_trace_55" BEL "u_udp_mac/u_udp_fsm/packet_trace_54" BEL "u_udp_mac/u_udp_fsm/packet_trace_53" BEL "u_udp_mac/u_udp_fsm/packet_trace_52" BEL "u_udp_mac/u_udp_fsm/packet_trace_51" BEL "u_udp_mac/u_udp_fsm/packet_trace_50" BEL "u_udp_mac/u_udp_fsm/packet_trace_49" BEL "u_udp_mac/u_udp_fsm/packet_trace_48" BEL "u_udp_mac/u_udp_fsm/packet_trace_47" BEL "u_udp_mac/u_udp_fsm/packet_trace_46" BEL "u_udp_mac/u_udp_fsm/packet_trace_45" BEL "u_udp_mac/u_udp_fsm/packet_trace_44" BEL "u_udp_mac/u_udp_fsm/packet_trace_43" BEL "u_udp_mac/u_udp_fsm/packet_trace_42" BEL "u_udp_mac/u_udp_fsm/packet_trace_41" BEL "u_udp_mac/u_udp_fsm/packet_trace_40" BEL "u_udp_mac/u_udp_fsm/packet_trace_37" BEL "u_udp_mac/u_udp_fsm/packet_trace_36" BEL "u_udp_mac/u_udp_fsm/packet_trace_35" BEL "u_udp_mac/u_udp_fsm/packet_trace_34" BEL "u_udp_mac/u_udp_fsm/packet_trace_33" BEL "u_udp_mac/u_udp_fsm/packet_trace_32" BEL "u_udp_mac/u_udp_fsm/packet_trace_31" BEL "u_udp_mac/u_udp_fsm/packet_trace_30" BEL "u_udp_mac/u_udp_fsm/packet_trace_29" BEL "u_udp_mac/u_udp_fsm/packet_trace_28" BEL "u_udp_mac/u_udp_fsm/packet_trace_27" BEL "u_udp_mac/u_udp_fsm/packet_trace_26" BEL "u_udp_mac/u_udp_fsm/packet_trace_25" BEL "u_udp_mac/u_udp_fsm/packet_trace_24" BEL "u_udp_mac/u_udp_fsm/packet_trace_23" BEL "u_udp_mac/u_udp_fsm/packet_trace_22" BEL "u_udp_mac/u_udp_fsm/packet_trace_21" BEL "u_udp_mac/u_udp_fsm/packet_trace_20" BEL "u_udp_mac/u_udp_fsm/packet_trace_19" BEL "u_udp_mac/u_udp_fsm/packet_trace_18" BEL "u_udp_mac/u_udp_fsm/packet_trace_17" BEL "u_udp_mac/u_udp_fsm/packet_trace_16" BEL "u_udp_mac/u_udp_fsm/packet_trace_15" BEL "u_udp_mac/u_udp_fsm/packet_trace_14" BEL "u_udp_mac/u_udp_fsm/packet_trace_13" BEL "u_udp_mac/u_udp_fsm/packet_trace_12" BEL "u_udp_mac/u_udp_fsm/packet_trace_11" BEL "u_udp_mac/u_udp_fsm/packet_trace_10" BEL "u_udp_mac/u_udp_fsm/packet_trace_9" BEL "u_udp_mac/u_udp_fsm/packet_trace_8" BEL "u_udp_mac/u_udp_fsm/prev_running_packet_5" BEL "u_udp_mac/u_udp_fsm/prev_running_packet_4" BEL "u_udp_mac/u_udp_fsm/prev_running_packet_3" BEL "u_udp_mac/u_udp_fsm/prev_running_packet_2" BEL "u_udp_mac/u_udp_fsm/prev_running_packet_1" BEL "u_udp_mac/u_udp_fsm/prev_running_packet_0" BEL "u_udp_mac/u_udp_fsm/tuser_15" BEL "u_udp_mac/u_udp_fsm/tuser_14" BEL "u_udp_mac/u_udp_fsm/tuser_13" BEL "u_udp_mac/u_udp_fsm/tuser_12" BEL "u_udp_mac/u_udp_fsm/tuser_11" BEL "u_udp_mac/u_udp_fsm/tuser_10" BEL "u_udp_mac/u_udp_fsm/tuser_9" BEL "u_udp_mac/u_udp_fsm/tuser_8" BEL "u_udp_mac/u_udp_fsm/tuser_7" BEL "u_udp_mac/u_udp_fsm/tuser_6" BEL "u_udp_mac/u_udp_fsm/tuser_5" BEL "u_udp_mac/u_udp_fsm/tuser_4" BEL "u_udp_mac/u_udp_fsm/tuser_3" BEL "u_udp_mac/u_udp_fsm/tuser_2" BEL "u_udp_mac/u_udp_fsm/tuser_1" BEL "u_udp_mac/u_udp_fsm/tuser_0" BEL "u_udp_mac/u_udp_fsm/size_rd_en" BEL "u_udp_mac/u_udp_fsm/last_packet" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[0].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[10].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[11].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[12].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[13].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[14].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[15].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[16].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[17].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[18].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[19].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[1].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[20].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[21].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[22].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[23].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[24].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[25].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[26].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[2].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[3].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[4].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[5].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[6].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[7].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[8].gv5.srl32" BEL "u_sru_40dtc_top/u_dtc_multiram/u_size_fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gsm.sm/gsm1.sm1/gram.gsms[9].gv5.srl32" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_pins<33>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_0/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_rx_dtc_1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram_pins<32>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_0/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_DtcRam_1/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<63>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<62>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<65>" PIN "u_sru_40dtc_top/u_dtc_multiram/u_fifo_udp_packet/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram_pins<64>"; PIN u_main_clk_gen/dtc_clkgen[39].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[39].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[38].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[38].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[37].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[37].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[36].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[36].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[35].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[35].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[34].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[34].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[33].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[33].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[32].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[32].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[31].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[31].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[30].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[30].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[29].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[29].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[28].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[28].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[27].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[27].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[26].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[26].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[25].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[25].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[24].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[24].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[23].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[23].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[22].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[22].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[21].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[21].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[20].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[20].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[19].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[19].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[18].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[18].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[17].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[17].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[16].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[16].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[15].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[15].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[14].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[14].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[13].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[13].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[12].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[12].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[11].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[11].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[10].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[10].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[9].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[9].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[8].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[8].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[7].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[7].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[6].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[6].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[5].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[5].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[4].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[4].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[3].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[3].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[2].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[2].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[1].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[1].ODDR_DTCCLK" PINNAME CK; PIN u_main_clk_gen/dtc_clkgen[0].ODDR_DTCCLK_pins<1> = BEL "u_main_clk_gen/dtc_clkgen[0].ODDR_DTCCLK" PINNAME CK; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout0 = PIN "u_main_clk_gen/dtc_clkgen[39].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[38].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[37].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[36].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[35].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[34].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[33].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[32].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[31].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[30].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[29].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[28].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[27].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[26].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[25].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[24].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[23].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[22].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[21].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[20].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[19].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[18].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[17].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[16].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[15].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[14].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[13].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[12].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[11].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[10].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[9].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[8].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[7].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[6].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[5].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[4].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[3].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[2].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[1].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[0].ODDR_DTCCLK_pins<1>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout1_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout0_0 = PIN "u_main_clk_gen/dtc_clkgen[39].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[38].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[37].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[36].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[35].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[34].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[33].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[32].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[31].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[30].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[29].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[28].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[27].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[26].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[25].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[24].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[23].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[22].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[21].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[20].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[19].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[18].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[17].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[16].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[15].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[14].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[13].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[12].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[11].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[10].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[9].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[8].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[7].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[6].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[5].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[4].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[3].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[2].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[1].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[0].ODDR_DTCCLK_pins<1>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout1_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout0_1 = PIN "u_main_clk_gen/dtc_clkgen[39].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[38].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[37].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[36].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[35].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[34].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[33].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[32].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[31].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[30].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[29].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[28].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[27].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[26].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[25].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[24].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[23].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[22].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[21].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[20].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[19].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[18].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[17].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[16].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[15].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[14].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[13].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[12].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[11].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[10].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[9].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[8].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[7].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[6].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[5].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[4].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[3].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[2].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[1].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[0].ODDR_DTCCLK_pins<1>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout1_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout0_2 = PIN "u_main_clk_gen/dtc_clkgen[39].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[38].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[37].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[36].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[35].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[34].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[33].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[32].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[31].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[30].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[29].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[28].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[27].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[26].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[25].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[24].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[23].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[22].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[21].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[20].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[19].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[18].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[17].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[16].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[15].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[14].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[13].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[12].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[11].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[10].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[9].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[8].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[7].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[6].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[5].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[4].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[3].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[2].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[1].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[0].ODDR_DTCCLK_pins<1>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout1_buf"; TIMEGRP u_main_clk_gen_USerClkSrc_USerClkGen_clkout0_3 = PIN "u_main_clk_gen/dtc_clkgen[39].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[38].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[37].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[36].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[35].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[34].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[33].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[32].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[31].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[30].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[29].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[28].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[27].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[26].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[25].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[24].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[23].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[22].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[21].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[20].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[19].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[18].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[17].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[16].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[15].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[14].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[13].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[12].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[11].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[10].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[9].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[8].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[7].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[6].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[5].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[4].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[3].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[2].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[1].ODDR_DTCCLK_pins<1>" PIN "u_main_clk_gen/dtc_clkgen[0].ODDR_DTCCLK_pins<1>" BEL "u_main_clk_gen/USerClkSrc/USerClkGen/clkout1_buf"; PIN u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate13_pins<1> = BEL "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate13" PINNAME REFCLK; PIN u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate12_pins<1> = BEL "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate12" PINNAME REFCLK; PIN u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate11_pins<1> = BEL "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate11" PINNAME REFCLK; PIN u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate10_pins<1> = BEL "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate10" PINNAME REFCLK; PIN u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate6_pins<1> = BEL "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate6" PINNAME REFCLK; PIN u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate5_pins<1> = BEL "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate5" PINNAME REFCLK; PIN u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate1_pins<1> = BEL "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate1" PINNAME REFCLK; PIN u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate0_pins<1> = BEL "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate0" PINNAME REFCLK; TIMEGRP u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout1 = BEL "u_main_clk_gen/USGclkMux/u_brdclk_pll/clkout2_buf" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate13_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate12_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate11_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate10_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate6_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate5_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate1_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate0_pins<1>"; TIMEGRP u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout1_0 = BEL "u_main_clk_gen/USGclkMux/u_brdclk_pll/clkout2_buf" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate13_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate12_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate11_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate10_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate6_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate5_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate1_pins<1>" PIN "u_sru_40dtc_top/IDELAYCTRL_inst_MapLib_replicate0_pins<1>"; TIMEGRP tx_metastable = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_fifo_full" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_state_FSM_FFd4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_col_window_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_col_window_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_retran_frame_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_tran_frame_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_txfer_tog_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen"; TIMEGRP tx_addr_wr = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_fifo_full" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_diff_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_start_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/ramgen"; TIMEGRP tx_fifo_rd_to_wr = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_retran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_tran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_col_window_pipe_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_txfer_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_retran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_tran_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_col_window_pipe_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/rd_txfer_tog"; TIMEGRP tx_fifo_wr_to_rd = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_ovflow_dst_rdy" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_state_FSM_FFd1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/frame_in_fifo_sync"; TIMEGRP tx_addr_rd = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/tx_fifo_i/wr_rd_addr_0"; TIMEGRP rx_fifo_wr_to_rd = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_store_frame_tog" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_tog"; TIMEGRP rx_metastable = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/rd_store_frame_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_0"; TIMEGRP rx_fifo_rd_to_wr = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_11" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/client_side_FIFO/rx_fifo_i/wr_rd_addr_gray_sync_0"; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/bufr_clk_ds_pins<2> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/bufr_clk_ds" PINNAME I; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<73> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i" PINNAME MGTREFCLKRX0; PIN u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<74> = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i" PINNAME MGTREFCLKTX0; PIN u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<73> = BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i" PINNAME MGTREFCLKRX0; PIN u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<74> = BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i" PINNAME MGTREFCLKTX0; TIMEGRP sfp_refclk = PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/bufr_clk_ds_pins<2>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<73>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<74>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<73>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<74>" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/bufr_clk_ds" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/reset_r_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/reset_r_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/reset_r_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/reset_r_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/plllkdet_sync" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/Mshreg_plllkdet_sync" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_0" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<73>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<74>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<73>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<74>"; TIMEGRP sfpRefClk = PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/bufr_clk_ds_pins<2>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<73>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<74>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<73>" PIN "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<74>" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/bufr_clk_ds" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/reset_r_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/reset_r_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/reset_r_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/reset_r_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/plllkdet_sync" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/Mshreg_plllkdet_sync" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_10" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_9" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_8" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_7" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_6" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_5" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_4" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_0" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_3" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_2" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_1" BEL "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_0" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<73>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<74>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<73>" PIN "u_udp_mac/sys_unit_inst/UDP_Complete_i/mac_block/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i_pins<74>"; TIMEGRP u_dcs_eth_top_u_xgbe2_ll_wrapper_u_xgbe2_locallink_xgbe2_block_inst_v6_gtxwizard_top_inst_clk_ds_i = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/plllkdet_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/Mshreg_plllkdet_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_0"; TIMEGRP u_dcs_eth_top_u_xgbe2_ll_wrapper_u_xgbe2_locallink_xgbe2_block_inst_v6_gtxwizard_top_inst_clk_ds_i_0 = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/plllkdet_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/Mshreg_plllkdet_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_0"; TIMEGRP u_dcs_eth_top_u_xgbe2_ll_wrapper_u_xgbe2_locallink_xgbe2_block_inst_v6_gtxwizard_top_inst_clk_ds_i_1 = BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/reset_r_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/plllkdet_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/Mshreg_plllkdet_sync" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_10" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_9" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_8" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_7" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_6" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_5" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_4" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_ctr_0" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_3" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_2" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_1" BEL "u_dcs_eth_top/u_xgbe2_ll_wrapper/u_xgbe2_locallink/xgbe2_block_inst/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/testdone_f_0"; PIN u_main_clk_gen/USGclkMux/u_brdclk_pll/mmcm_adv_inst_pins<2> = BEL "u_main_clk_gen/USGclkMux/u_brdclk_pll/mmcm_adv_inst" PINNAME CLKIN1; TIMEGRP brd_clk_100m = PIN "u_main_clk_gen/USGclkMux/u_brdclk_pll/mmcm_adv_inst_pins<2>"; NET "u_main_clk_gen/USerClkSrc/USerClkGen/clkout4" MAXSKEW = 0.1 ns; NET "u_main_clk_gen/USerClkSrc/USerClkGen/clkout2" MAXSKEW = 0.1 ns; NET "u_main_clk_gen/USerClkSrc/USerClkGen/clkout1" MAXSKEW = 0.1 ns; NET "u_main_clk_gen/USerClkSrc/USerClkGen/clkout0" MAXSKEW = 0.1 ns; NET "u_main_clk_gen/USerClkSrc/USerClkGen/clkout3" MAXSKEW = 0.1 ns; TS_sfp_refclk = PERIOD TIMEGRP "sfp_refclk" 8 ns HIGH 50% INPUT_JITTER 0.1 ns; TS_u_dcs_eth_top_EMACORE_u_xgbe2_ll_wrapper_clk125_o = PERIOD TIMEGRP "u_dcs_eth_top/u_xgbe2_ll_wrapper/clk125_o" 8 ns HIGH 50% INPUT_JITTER 0.1 ns; TS_tx_fifo_rd_to_wr = MAXDELAY FROM TIMEGRP "tx_fifo_rd_to_wr" TO TIMEGRP "u_xgbe2_ll_wrapper_clk125_o" 8 ns DATAPATHONLY; TS_tx_fifo_wr_to_rd = MAXDELAY FROM TIMEGRP "tx_fifo_wr_to_rd" TO TIMEGRP "u_xgbe2_ll_wrapper_clk125_o" 8 ns DATAPATHONLY; TS_tx_meta_protect = MAXDELAY FROM TIMEGRP "tx_metastable" 5 ns DATAPATHONLY; TS_tx_fifo_addr = MAXDELAY FROM TIMEGRP "tx_addr_rd" TO TIMEGRP "tx_addr_wr" 10 ns; TS_rx_fifo_wr_to_rd = MAXDELAY FROM TIMEGRP "rx_fifo_wr_to_rd" TO TIMEGRP "u_xgbe2_ll_wrapper_clk125_o" 8 ns DATAPATHONLY; TS_rx_fifo_rd_to_wr = MAXDELAY FROM TIMEGRP "rx_fifo_rd_to_wr" TO TIMEGRP "u_xgbe2_ll_wrapper_clk125_o" 8 ns DATAPATHONLY; TS_rx_meta_protect = MAXDELAY FROM TIMEGRP "rx_metastable" 5 ns; TS_brd_clk_100m = PERIOD TIMEGRP "brd_clk_100m" 10 ns HIGH 50% INPUT_JITTER 0.5 ns; TS_clk_40m = PERIOD TIMEGRP "clk_40m" 25 ns HIGH 50% INPUT_JITTER 0.5 ns; ts_sfpRefClk = PERIOD TIMEGRP "sfpRefClk" 8 ns HIGH 50%; TS_sfpClkOut = PERIOD TIMEGRP "sfpClkOut" 8 ns HIGH 50%; TS_u_dcs_eth_top_u_xgbe2_ll_wrapper_u_xgbe2_locallink_xgbe2_block_inst_v6_gtxwizard_top_inst_clk_ds_i_0 = PERIOD TIMEGRP "u_dcs_eth_top_u_xgbe2_ll_wrapper_u_xgbe2_locallink_xgbe2_block_inst_v6_gtxwizard_top_inst_clk_ds_i_0" TS_sfp_refclk HIGH 50% INPUT_JITTER 0.1 ns; TS_u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout1_0 = PERIOD TIMEGRP "u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout1_0" TS_brd_clk_100m / 2 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout0_0 = PERIOD TIMEGRP "u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout0_0" TS_brd_clk_100m / 0.4 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_UTLUSyncPLL_clkout0 = PERIOD TIMEGRP "u_main_clk_gen_UTLUSyncPLL_clkout0" TS_clk_40m HIGH 50% INPUT_JITTER 0.5 ns; TS_u_dcs_eth_top_u_xgbe2_ll_wrapper_u_xgbe2_locallink_xgbe2_block_inst_v6_gtxwizard_top_inst_clk_ds_i_1 = PERIOD TIMEGRP "u_dcs_eth_top_u_xgbe2_ll_wrapper_u_xgbe2_locallink_xgbe2_block_inst_v6_gtxwizard_top_inst_clk_ds_i_1" ts_sfpRefClk HIGH 50%; TS_clk10m_i_1 = PERIOD TIMEGRP "clk10m_i_1" TS_u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout0_0 * 4 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout3_1 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout3_1" TS_u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout0_0 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout1_1 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout1_1" TS_u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout0_0 / 0.25 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout0_1 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout0_1" TS_u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout0_0 PHASE -6.25 ns HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout4_1 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout4_1" TS_u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout0_0 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout2_1 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout2_1" TS_u_main_clk_gen_USGclkMux_u_brdclk_pll_clkout0_0 / 0.125 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout3_2 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout3_2" TS_u_main_clk_gen_UTLUSyncPLL_clkout0 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout1_2 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout1_2" TS_u_main_clk_gen_UTLUSyncPLL_clkout0 / 0.25 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout0_2 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout0_2" TS_u_main_clk_gen_UTLUSyncPLL_clkout0 PHASE -6.25 ns HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout4_2 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout4_2" TS_u_main_clk_gen_UTLUSyncPLL_clkout0 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout2_2 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout2_2" TS_u_main_clk_gen_UTLUSyncPLL_clkout0 / 0.125 HIGH 50% INPUT_JITTER 0.5 ns; TS_clk10m_i = PERIOD TIMEGRP "clk10m_i" TS_clk_40m * 4 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout3 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout3" TS_clk_40m HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout1 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout1" TS_clk_40m / 0.25 HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout0 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout0" TS_clk_40m PHASE -6.25 ns HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout4 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout4" TS_clk_40m HIGH 50% INPUT_JITTER 0.5 ns; TS_u_main_clk_gen_USerClkSrc_USerClkGen_clkout2 = PERIOD TIMEGRP "u_main_clk_gen_USerClkSrc_USerClkGen_clkout2" TS_clk_40m / 0.125 HIGH 50% INPUT_JITTER 0.5 ns; PIN LedIndicator<1>1_pins<4> = BEL "LedIndicator<1>1" PINNAME O6; PIN LedIndicator<0>1_pins<3> = BEL "LedIndicator<0>1" PINNAME O5; PIN LedIndicator<2>1_pins<4> = BEL "LedIndicator<2>1" PINNAME O6; PIN LedIndicator<3>1_pins<4> = BEL "LedIndicator<3>1" PINNAME O5; PIN LedIndicator_3_OBUF_pins<1> = BEL "LedIndicator_3_OBUF" PINNAME OUT; PIN LedIndicator_2_OBUF_pins<1> = BEL "LedIndicator_2_OBUF" PINNAME OUT; PIN LedIndicator_1_OBUF_pins<1> = BEL "LedIndicator_1_OBUF" PINNAME OUT; PIN LedIndicator_0_OBUF_pins<1> = BEL "LedIndicator_0_OBUF" PINNAME OUT; PIN spare_11_OBUF_pins<1> = BEL "spare_11_OBUF" PINNAME OUT; PIN spare_10_OBUF_pins<1> = BEL "spare_10_OBUF" PINNAME OUT; PIN spare_9_OBUF_pins<1> = BEL "spare_9_OBUF" PINNAME OUT; PIN spare_8_OBUF_pins<1> = BEL "spare_8_OBUF" PINNAME OUT; PIN spare_7_OBUF_pins<1> = BEL "spare_7_OBUF" PINNAME OUT; PIN spare_6_OBUF_pins<1> = BEL "spare_6_OBUF" PINNAME OUT; PIN spare_5_OBUF_pins<1> = BEL "spare_5_OBUF" PINNAME OUT; PIN spare_4_OBUF_pins<1> = BEL "spare_4_OBUF" PINNAME OUT; PIN MMCM_PHASE_CALIBRATION_ML_LUT2_31_pins<2> = BEL "MMCM_PHASE_CALIBRATION_ML_LUT2_31" PINNAME O6; PIN MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_30_pins<2> = BEL "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_30" PINNAME Q; PIN MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_29_pins<2> = BEL "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_29" PINNAME Q; PIN MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_28_pins<2> = BEL "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_28" PINNAME Q; PIN MMCM_PHASE_CALIBRATION_ML_LDCPE_I0_27_pins<0> = BEL "MMCM_PHASE_CALIBRATION_ML_LDCPE_I0_27" PINNAME CK; PIN MMCM_PHASE_CALIBRATION_ML_LUT2_39_pins<2> = BEL "MMCM_PHASE_CALIBRATION_ML_LUT2_39" PINNAME O6; PIN MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_37_pins<2> = BEL "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_37" PINNAME Q; PIN MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_36_pins<2> = BEL "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_36" PINNAME Q; PIN MMCM_PHASE_CALIBRATION_ML_LDCPE_I0_35_pins<0> = BEL "MMCM_PHASE_CALIBRATION_ML_LDCPE_I0_35" PINNAME CK; PIN MMCM_PHASE_CALIBRATION_ML_LUT2_47_pins<2> = BEL "MMCM_PHASE_CALIBRATION_ML_LUT2_47" PINNAME O6; PIN MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_46_pins<3> = BEL "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_46" PINNAME SR; PIN MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_46_pins<2> = BEL "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_46" PINNAME Q; PIN MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_45_pins<3> = BEL "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_45" PINNAME SR; PIN MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_45_pins<2> = BEL "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_45" PINNAME Q; PIN MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_44_pins<3> = BEL "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_44" PINNAME SR; PIN MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_44_pins<2> = BEL "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_44" PINNAME Q; PIN MMCM_PHASE_CALIBRATION_ML_LDCPE_I0_43_pins<0> = BEL "MMCM_PHASE_CALIBRATION_ML_LDCPE_I0_43" PINNAME CK; PIN "LedIndicator<1>1_pins<4>" TIG; PIN "LedIndicator<0>1_pins<3>" TIG; PIN "LedIndicator<2>1_pins<4>" TIG; PIN "LedIndicator<3>1_pins<4>" TIG; PIN "LedIndicator_3_OBUF_pins<1>" TIG; PIN "LedIndicator_2_OBUF_pins<1>" TIG; PIN "LedIndicator_1_OBUF_pins<1>" TIG; PIN "LedIndicator_0_OBUF_pins<1>" TIG; PIN "spare_11_OBUF_pins<1>" TIG; PIN "spare_10_OBUF_pins<1>" TIG; PIN "spare_9_OBUF_pins<1>" TIG; PIN "spare_8_OBUF_pins<1>" TIG; PIN "spare_7_OBUF_pins<1>" TIG; PIN "spare_6_OBUF_pins<1>" TIG; PIN "spare_5_OBUF_pins<1>" TIG; PIN "spare_4_OBUF_pins<1>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_LUT2_31_pins<2>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_30_pins<2>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_29_pins<2>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_28_pins<2>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_LDCPE_I0_27_pins<0>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_LUT2_39_pins<2>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_37_pins<2>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_36_pins<2>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_LDCPE_I0_35_pins<0>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_LUT2_47_pins<2>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_46_pins<3>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_46_pins<2>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_45_pins<3>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_45_pins<2>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_44_pins<3>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_FDCPE_I0_44_pins<2>" TIG; PIN "MMCM_PHASE_CALIBRATION_ML_LDCPE_I0_43_pins<0>" TIG; COMP "htrig_number_p" OFFSET = IN 12 ns VALID 13 ns BEFORE COMP "tlu_clk40_p" "RISING"; COMP "htrig_nim" OFFSET = IN 12 ns VALID 13 ns BEFORE COMP "tlu_clk40_p" "RISING"; OFFSET = IN 18 ns VALID 23 ns BEFORE COMP "tlu_clk40_p" "RISING"; OFFSET = OUT 8 ns VALID 17 ns AFTER COMP "tlu_clk40_p" "RISING"; SCHEMATIC END;